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Commit 0bb2ef61 authored by David Wu's avatar David Wu Committed by Heiko Stuebner
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arm64: dts: rockchip: Add pwm nodes for rk3328 



There are 4 pwm channels built in rk3328 soc, need to configure
the both APB clock and bus clock.

Signed-off-by: default avatarDavid Wu <david.wu@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent a4c6bbcb

arch/arm64/boot/dts/rockchip/rk3328.dtsi

+45 −0
Original line number Diff line number Diff line
@@ -406,6 +406,51 @@ 
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

	};



	pwm0: pwm@ff1b0000 {

		compatible = "rockchip,rk3328-pwm";

		reg = <0x0 0xff1b0000 0x0 0x10>;

		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;

		clock-names = "pwm", "pclk";

		pinctrl-names = "default";

		pinctrl-0 = <&pwm0_pin>;

		#pwm-cells = <3>;

		status = "disabled";

	};



	pwm1: pwm@ff1b0010 {

		compatible = "rockchip,rk3328-pwm";

		reg = <0x0 0xff1b0010 0x0 0x10>;

		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;

		clock-names = "pwm", "pclk";

		pinctrl-names = "default";

		pinctrl-0 = <&pwm1_pin>;

		#pwm-cells = <3>;

		status = "disabled";

	};



	pwm2: pwm@ff1b0020 {

		compatible = "rockchip,rk3328-pwm";

		reg = <0x0 0xff1b0020 0x0 0x10>;

		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;

		clock-names = "pwm", "pclk";

		pinctrl-names = "default";

		pinctrl-0 = <&pwm2_pin>;

		#pwm-cells = <3>;

		status = "disabled";

	};



	pwm3: pwm@ff1b0030 {

		compatible = "rockchip,rk3328-pwm";

		reg = <0x0 0xff1b0030 0x0 0x10>;

		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;

		clock-names = "pwm", "pclk";

		pinctrl-names = "default";

		pinctrl-0 = <&pwmir_pin>;

		#pwm-cells = <3>;

		status = "disabled";

	};



	thermal-zones {

		soc_thermal: soc-thermal {

			polling-delay-passive = <20>;