Merge "Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14" (0b5a4b47) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/drm/msm/sde/sde_hw_interrupts.c

+0 −4

Original line number	Diff line number	Diff line
		@@ -805,8 +805,6 @@ static const struct sde_irq_type sde_irq_map[] = {
		SDE_INTR_INTF_TEAR_WR_PTR, 10},
		{ SDE_IRQ_TYPE_INTF_TEAR_RD_PTR, INTF_1,
		SDE_INTR_INTF_TEAR_RD_PTR, 10},
		{ SDE_IRQ_TYPE_INTF_TEAR_TE_CHECK, INTF_1,
		SDE_INTR_INTF_TEAR_TE_DETECTED, 10},
		/* irq_idx: 323 */
		{ SDE_IRQ_TYPE_INTF_TEAR_TEAR_CHECK, INTF_1,
		SDE_INTR_INTF_TEAR_TEAR_DETECTED, 10},
		@@ -854,8 +852,6 @@ static const struct sde_irq_type sde_irq_map[] = {
		SDE_INTR_INTF_TEAR_WR_PTR, 11},
		{ SDE_IRQ_TYPE_INTF_TEAR_RD_PTR, INTF_2,
		SDE_INTR_INTF_TEAR_RD_PTR, 11},
		{ SDE_IRQ_TYPE_INTF_TEAR_TE_CHECK, INTF_2,
		SDE_INTR_INTF_TEAR_TE_DETECTED, 11},
		/* irq_idx: 355 */
		{ SDE_IRQ_TYPE_INTF_TEAR_TEAR_CHECK, INTF_2,
		SDE_INTR_INTF_TEAR_TEAR_DETECTED, 11},

drivers/gpu/drm/msm/sde_dbg.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -4046,6 +4046,11 @@ static ssize_t sde_evtlog_dump_read(struct file file, char __user buff,

		len = sde_evtlog_dump_to_buffer(sde_dbg_base.evtlog, evtlog_buf,
		SDE_EVTLOG_BUF_MAX, true);
		if (len < 0 \|\| len > count) {
		pr_err("len is more than user buffer size");
		return 0;
		}

		if (copy_to_user(buff, evtlog_buf, len))
		return -EFAULT;
		*ppos += len;

drivers/gpu/drm/msm/sde_rsc_hw.c

+100 −21

Original line number	Diff line number	Diff line
		@@ -99,6 +99,13 @@
		#define MAX_CHECK_LOOPS 500
		#define POWER_CTRL_BIT_12 12

		#define SDE_RSC_MODE_0_VAL 0
		#define SDE_RSC_MODE_1_VAL 1
		#define MAX_MODE2_ENTRY_TRY 3

		#define SDE_RSC_REV_1 0x1
		#define SDE_RSC_REV_2 0x2

		static void rsc_event_trigger(struct sde_rsc_priv *rsc, uint32_t event_type)
		{
		struct sde_rsc_event *event;
		@@ -453,11 +460,13 @@ static int sde_rsc_mode2_exit(struct sde_rsc_priv *rsc,
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_CTRL,
		reg, rsc->debug_mode);

		if (rsc->version < SDE_RSC_REV_2) {
		reg = dss_reg_r(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
		rsc->debug_mode);
		reg \|= BIT(13);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
		reg, rsc->debug_mode);
		}

		/* make sure that mode-2 exit before wait*/
		wmb();
		@@ -476,36 +485,31 @@ static int sde_rsc_mode2_exit(struct sde_rsc_priv *rsc,
		usleep_range(10, 100);
		}

		if (rsc->version < SDE_RSC_REV_2) {
		reg = dss_reg_r(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
		rsc->debug_mode);
		reg &= ~BIT(13);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
		reg, rsc->debug_mode);
		}

		if (rc)
		pr_err("vdd reg is not enabled yet\n");

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0,
		0x3, rsc->debug_mode);

		rsc_event_trigger(rsc, SDE_RSC_EVENT_POST_CORE_RESTORE);

		return rc;
		}

		static int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc)
		static int sde_rsc_mode2_entry_trigger(struct sde_rsc_priv *rsc)
		{
		int rc;
		int count, wrapper_status;
		unsigned long reg;

		if (rsc->power_collapse_block)
		return -EINVAL;

		rc = regulator_set_mode(rsc->fs, REGULATOR_MODE_FAST);
		if (rc) {
		pr_err("vdd reg fast mode set failed rc:%d\n", rc);
		return rc;
		}

		rsc_event_trigger(rsc, SDE_RSC_EVENT_PRE_CORE_PC);

		/* update qtimers to high during clk & video mode state */
		if ((rsc->current_state == SDE_RSC_VID_STATE) \|\|
		(rsc->current_state == SDE_RSC_CLK_STATE)) {
		@@ -550,15 +554,90 @@ static int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc)
		usleep_range(10, 100);
		}

		return rc;
		}

		static void sde_rsc_reset_mode_0_1(struct sde_rsc_priv *rsc)
		{
		u32 seq_busy, current_mode, curr_inst_addr;

		seq_busy = dss_reg_r(&rsc->drv_io, SDE_RSCC_SEQ_BUSY_DRV0,
		rsc->debug_mode);
		current_mode = dss_reg_r(&rsc->drv_io, SDE_RSCC_SOLVER_STATUS2_DRV0,
		rsc->debug_mode);
		curr_inst_addr = dss_reg_r(&rsc->drv_io, SDE_RSCC_SEQ_PROGRAM_COUNTER,
		rsc->debug_mode);
		SDE_EVT32(seq_busy, current_mode, curr_inst_addr);

		if (seq_busy && (current_mode == SDE_RSC_MODE_0_VAL \|\|
		current_mode == SDE_RSC_MODE_1_VAL)) {
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_HI,
		0xffffff, rsc->debug_mode);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,
		0xffffffff, rsc->debug_mode);
		/* unstick f1 qtimer */
		wmb();

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_HI,
		0x0, rsc->debug_mode);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,
		0x0, rsc->debug_mode);
		/* manually trigger f1 qtimer interrupt */
		wmb();

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_HI,
		0xffffff, rsc->debug_mode);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_LO,
		0xffffffff, rsc->debug_mode);
		/* unstick f0 qtimer */
		wmb();

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_HI,
		0x0, rsc->debug_mode);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_LO,
		0x0, rsc->debug_mode);
		/* manually trigger f0 qtimer interrupt */
		wmb();
		}
		}

		static int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc)
		{
		int rc = 0, i;
		u32 reg;

		if (rsc->power_collapse_block)
		return -EINVAL;

		rc = regulator_set_mode(rsc->fs, REGULATOR_MODE_FAST);
		if (rc) {
		pr_err("vdd reg fast mode set failed rc:%d\n", rc);
		return rc;
		}

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0,
		0x7, rsc->debug_mode);
		rsc_event_trigger(rsc, SDE_RSC_EVENT_PRE_CORE_PC);

		for (i = 0; i <= MAX_MODE2_ENTRY_TRY; i++) {
		rc = sde_rsc_mode2_entry_trigger(rsc);
		if (!rc)
		break;

		reg = dss_reg_r(&rsc->drv_io,
		SDE_RSCC_SEQ_PROGRAM_COUNTER, rsc->debug_mode);
		pr_err("mdss gdsc power down failed, instruction:0x%x, rc:%d\n",
		reg, rc);
		SDE_EVT32(rc, reg, SDE_EVTLOG_ERROR);
		goto end;

		/* avoid touching f1 qtimer for last try */
		if (i != MAX_MODE2_ENTRY_TRY)
		sde_rsc_reset_mode_0_1(rsc);
		}

		if (rc)
		goto end;

		if ((rsc->current_state == SDE_RSC_VID_STATE) \|\|
		(rsc->current_state == SDE_RSC_CLK_STATE)) {
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_OVERRIDE_CTRL,
		@@ -632,7 +711,7 @@ static int sde_rsc_state_update(struct sde_rsc_priv *rsc,

		reg = dss_reg_r(&rsc->wrapper_io,
		SDE_RSCC_WRAPPER_OVERRIDE_CTRL, rsc->debug_mode);
		reg &= ~(BIT(8) \| BIT(0));
		reg &= ~BIT(0);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_OVERRIDE_CTRL,
		reg, rsc->debug_mode);
		/* make sure that solver mode is disabled */
		@@ -671,7 +750,7 @@ int rsc_hw_init(struct sde_rsc_priv *rsc)
		goto end;
		}

		if (rsc->version == 2)
		if (rsc->version == SDE_RSC_REV_2)
		rc = rsc_hw_seq_memory_init_v2(rsc);
		else
		rc = rsc_hw_seq_memory_init(rsc);