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Commit 0b3ea77c authored by Sayali Lokhande's avatar Sayali Lokhande
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ARM: dts: msm: Enable UFS support on sdmmagpie



Enable UFS support on sdmmagpie platform.

Change-Id: I59fd10b8de0ae3b6d4420b599f2f8c5cf756539e
Signed-off-by: default avatarSayali Lokhande <sayalil@codeaurora.org>
parent 080a3047
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+26 −0
Original line number Diff line number Diff line
@@ -16,3 +16,29 @@
&qupv3_se8_2uart {
	status = "ok";
};

&ufsphy_mem {
	compatible = "qcom,ufs-phy-qmp-v3";

	vdda-phy-supply = <&pm6150_l4>; /* 0.88v */
	vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */
	vdda-phy-max-microamp = <62900>;
	vdda-pll-max-microamp = <18300>;

	status = "ok";
};

&ufshc_mem {
	vdd-hba-supply = <&ufs_phy_gdsc>;
	vdd-hba-fixed-regulator;
	vcc-supply = <&pm6150_l19>;
	vcc-voltage-level = <2950000 2960000>;
	vccq2-supply = <&pm6150_l12>;
	vcc-max-microamp = <600000>;
	vccq2-max-microamp = <600000>;

	qcom,vddp-ref-clk-supply = <&pm6150l_l3>;
	qcom,vddp-ref-clk-max-microamp = <100>;

	status = "ok";
};
+46 −0
Original line number Diff line number Diff line
@@ -20,6 +20,52 @@
		interrupt-controller;
		#interrupt-cells = <2>;

		ufs_dev_reset_assert: ufs_dev_reset_assert {
			config {
				pins = "ufs_reset";
				bias-pull-down;		/* default: pull down */
				/*
				 * UFS_RESET driver strengths are having
				 * different values/steps compared to typical
				 * GPIO drive strengths.
				 *
				 * Following table clarifies:
				 *
				 * HDRV value | UFS_RESET | Typical GPIO
				 *   (dec)    |   (mA)    |    (mA)
				 *     0      |   0.8     |    2
				 *     1      |   1.55    |    4
				 *     2      |   2.35    |    6
				 *     3      |   3.1     |    8
				 *     4      |   3.9     |    10
				 *     5      |   4.65    |    12
				 *     6      |   5.4     |    14
				 *     7      |   6.15    |    16
				 *
				 * POR value for UFS_RESET HDRV is 3 which means
				 * 3.1mA and we want to use that. Hence just
				 * specify 8mA to "drive-strength" binding and
				 * that should result into writing 3 to HDRV
				 * field.
				 */
				drive-strength = <8>;	/* default: 3.1 mA */
				output-low; /* active low reset */
			};
		};

		ufs_dev_reset_deassert: ufs_dev_reset_deassert {
			config {
				pins = "ufs_reset";
				bias-pull-down;		/* default: pull down */
				/*
				 * default: 3.1 mA
				 * check comments under ufs_dev_reset_assert
				 */
				drive-strength = <8>;
				output-high; /* active low reset */
			};
		};

		/* QUPv3 South SE mappings */
		/* SE 0 pin mappings */
		qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+26 −0
Original line number Diff line number Diff line
@@ -16,3 +16,29 @@
&qupv3_se8_2uart {
	status = "ok";
};

&ufsphy_mem {
	compatible = "qcom,ufs-phy-qmp-v3";

	vdda-phy-supply = <&pm6150_l4>; /* 0.88v */
	vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */
	vdda-phy-max-microamp = <62900>;
	vdda-pll-max-microamp = <18300>;

	status = "ok";
};

&ufshc_mem {
	vdd-hba-supply = <&ufs_phy_gdsc>;
	vdd-hba-fixed-regulator;
	vcc-supply = <&pm6150_l19>;
	vcc-voltage-level = <2950000 2960000>;
	vccq2-supply = <&pm6150_l12>;
	vcc-max-microamp = <600000>;
	vccq2-max-microamp = <600000>;

	qcom,vddp-ref-clk-supply = <&pm6150l_l3>;
	qcom,vddp-ref-clk-max-microamp = <100>;

	status = "ok";
};
+35 −0
Original line number Diff line number Diff line
@@ -92,6 +92,41 @@
	status = "disabled";
};

&ufsphy_mem {
	compatible = "qcom,ufs-phy-qrbtc-sdm845";

	vdda-phy-supply = <&pm6150_l4>; /* 0.88v */
	vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */
	vdda-phy-max-microamp = <62900>;
	vdda-pll-max-microamp = <18300>;

	status = "ok";
};

&ufshc_mem {
	limit-tx-hs-gear = <1>;
	limit-rx-hs-gear = <1>;
	scsi-cmd-timeout = <300000>;

	vdd-hba-supply = <&ufs_phy_gdsc>;
	vdd-hba-fixed-regulator;
	vcc-supply = <&pm6150_l19>;
	vccq2-supply = <&pm6150_l12>;
	vcc-max-microamp = <600000>;
	vccq2-max-microamp = <600000>;

	qcom,vddp-ref-clk-supply = <&pm6150l_l3>;
	qcom,vddp-ref-clk-max-microamp = <100>;
	qcom,vddp-ref-clk-min-uV = <1200000>;
	qcom,vddp-ref-clk-max-uV = <1200000>;

	qcom,disable-lpm;
	rpm-level = <0>;
	spm-level = <0>;
	status = "ok";
};


&qupv3_se8_2uart {
	status = "ok";
};
+106 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@
		hsuart0 = &qupv3_se3_4uart;
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
	};

	cpus {
@@ -1592,6 +1593,111 @@
		status = "disabled";
	};

	ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xddc>; /* PHY regs */
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <1>;

		clock-names = "ref_clk_src",
			"ref_clk",
			"ref_aux_clk";
		clocks = <&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;

		status = "disabled";
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x3000>;
		interrupts = <0 265 0>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";

		lanes-per-direction = <1>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */
		spm-level = <5>;

		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk";
		clocks =
			<&clock_gcc GCC_UFS_PHY_AXI_CLK>,
			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
		freq-table-hz =
			<50000000 240000000>,
			<0 0>,
			<0 0>,
			<37500000 150000000>,
			<75000000 300000000>,
			<0 0>,
			<0 0>,
			<0 0>;

		qcom,msm-bus,name = "ufshc_mem";
		qcom,msm-bus,num-cases = <12>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
		/*
		 * During HS G3 UFS runs at nominal voltage corner, vote
		 * higher bandwidth to push other buses in the data path
		 * to run at nominal to achieve max throughput.
		 * 4GBps pushes BIMC to run at nominal.
		 * 200MBps pushes CNOC to run at nominal.
		 * Vote for half of this bandwidth for HS G3 1-lane.
		 * For max bandwidth, vote high enough to push the buses
		 * to run in turbo voltage corner.
		 */
		<123 512 0 0>, <1 757 0 0>,          /* No vote */
		<123 512 922 0>, <1 757 1000 0>,     /* PWM G1 */
		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G2 */
		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G3 */
		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G4 */
		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */
		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */
		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RA */
		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */
		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */
		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RB */
		<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
		"MAX";

		/* PM QoS */
		qcom,pm-qos-cpu-groups = <0x3f 0xC0>;
		qcom,pm-qos-cpu-group-latency-us = <67 67>;
		qcom,pm-qos-default-cpu = <0>;

		pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
		pinctrl-0 = <&ufs_dev_reset_assert>;
		pinctrl-1 = <&ufs_dev_reset_deassert>;

		resets = <&clock_gcc GCC_UFS_PHY_BCR>;
		reset-names = "core_reset";
		non-removable;

		status = "disabled";
	};

	qcom,lpass@62400000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x62400000 0x00100>;