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Commit 0b29e375 authored by Patrick Daly's avatar Patrick Daly Committed by Sudarshan Rajagopalan
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iommu: arm-smmu: Fix QSMMUV500 system cache quirk 



Having page tables which are non coherent, but cached in a system
cache requires SH=Non-Shareable. This applies to the qsmmuv500 model.
For data buffers SH=Non-Shareable is not required.

Change-Id: I51ff72be3e506df481628bdc7d3c069ff518ad0a
Signed-off-by: default avatarPatrick Daly <pdaly@codeaurora.org>
Signed-off-by: default avatarSudarshan Rajagopalan <sudaraja@codeaurora.org>
parent 387e9dc0

drivers/iommu/arm-smmu.c

+3 −0
Original line number Diff line number Diff line
@@ -1676,6 +1676,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, 
		quirks |= IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT;

	if (is_iommu_pt_coherent(smmu_domain))

		quirks |= IO_PGTABLE_QUIRK_NO_DMA;

	if ((quirks & IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT) &&

		(smmu->model == QCOM_SMMUV500))

		quirks |= IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE;



	ret = arm_smmu_alloc_cb(domain, smmu, dev);

	if (ret < 0)

drivers/iommu/io-pgtable-arm.c

+7 −1
Original line number Diff line number Diff line
@@ -1116,7 +1116,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) 


	if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS

			  | IO_PGTABLE_QUIRK_NO_DMA

			  | IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT))

			  | IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT

			  | IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE))

		return NULL;



	data = arm_lpae_alloc_pgtable(cfg);
@@ -1128,6 +1129,11 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) 
		reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) |

			(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |

			(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);

	else if ((cfg->quirks & IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT) &&

		(cfg->quirks & IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE))

		reg = (ARM_LPAE_TCR_SH_NS << ARM_LPAE_TCR_SH0_SHIFT) |

			(ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) |

			(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);

	else if (cfg->quirks & IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT)

		reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) |

			(ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) |

drivers/iommu/io-pgtable.h

+8 −0
Original line number Diff line number Diff line
@@ -81,6 +81,13 @@ struct io_pgtable_cfg { 
	 *	be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a

	 *	software-emulated IOMMU), such that pagetable updates need not

	 *	be treated as explicit DMA data.

	 *



	 * IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE:

	 *	Having page tables which are non coherent, but cached in a

	 *	system cache requires SH=Non-Shareable. This applies to the

	 *	qsmmuv500 model. For data buffers SH=Non-Shareable is not

	 *	required.



	 * IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT: Override the attributes

	 *	set in TCR for the page table walker. Use attributes specified
@@ -92,6 +99,7 @@ struct io_pgtable_cfg { 
	#define IO_PGTABLE_QUIRK_TLBI_ON_MAP	BIT(2)

	#define IO_PGTABLE_QUIRK_ARM_MTK_4GB	BIT(3)

	#define IO_PGTABLE_QUIRK_NO_DMA		BIT(4)

	#define IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE BIT(5)

	#define IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT	BIT(6)

	unsigned long			quirks;

	unsigned long			pgsize_bitmap;