Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0b07ec3e authored by Manaf Meethalavalappu Pallikunhi's avatar Manaf Meethalavalappu Pallikunhi Committed by Gerrit - the friendly Code Review server
Browse files

ARM: dts: msm: Add LMH-DCVSh configuration for SDMMAGPIE 



Add LMH-DCVSh hardware configuration like debug interrupt and cluster
affinity value for SDMMAGPIE. It enables CPU cooling devices for this
target. Add the CPU to LMH-DCVSh hardware mapping, along with the
LMH thermal throttling thermal zone definition.

Change-Id: Iac8fa2f0ce4b8178490c7c30225f559d2c6eab05
Signed-off-by: default avatarManaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
parent 0a56f56a

arch/arm64/boot/dts/qcom/sdmmagpie-thermal.dtsi

+52 −0
Original line number Diff line number Diff line
@@ -13,6 +13,28 @@ 


#include <dt-bindings/thermal/thermal.h>



&clock_cpucc {

	#address-cells = <1>;

	#size-cells = <1>;

	lmh_dcvs0: qcom,limits-dcvs@18358800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <0>;

		reg = <0x18358800 0x1000>,

			<0x18323000 0x1000>;

		#thermal-sensor-cells = <0>;

	};



	lmh_dcvs1: qcom,limits-dcvs@18350800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0x18350800 0x1000>,

			<0x18325800 0x1000>;

		#thermal-sensor-cells = <0>;

	};

};



&soc {

	qmi-tmd-devices {

		compatible = "qcom,qmi-cooling-devices";
@@ -639,4 +661,34 @@ 
			};

		};

	};



	lmh-dcvs-00 {

		polling-delay-passive = <0>;

		polling-delay = <0>;

		thermal-governor = "user_space";

		thermal-sensors = <&lmh_dcvs0>;



		trips {

			active-config {

				temperature = <95000>;

				hysteresis = <30000>;

				type = "passive";

			};

		};

	};



	lmh-dcvs-01 {

		polling-delay-passive = <0>;

		polling-delay = <0>;

		thermal-governor = "user_space";

		thermal-sensors = <&lmh_dcvs1>;



		trips {

			active-config {

				temperature = <95000>;

				hysteresis = <30000>;

				type = "passive";

			};

		};

	};

};

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -53,6 +53,8 @@ 
			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -88,6 +90,8 @@ 
			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_100>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_100: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -118,6 +122,8 @@ 
			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_200>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_200: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -147,6 +153,8 @@ 
			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_300>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_300: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -176,6 +184,8 @@ 
			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_400>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_400: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -205,6 +215,8 @@ 
			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_500>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_500: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -234,6 +246,8 @@ 
			enable-method = "psci";

			cache-size = <0x10000>;

			next-level-cache = <&L2_600>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			L2_600: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;
@@ -272,6 +286,8 @@ 
			enable-method = "psci";

			cache-size = <0x10000>;

			next-level-cache = <&L2_700>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			L2_700: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;