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Commit 0a7eec7f authored by Peter De Schrijver's avatar Peter De Schrijver
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clk: tegra124: init table updates 



Ensure some clocks critical for system operation are always. Also enable csite
for JTAG debugging and set the tsensor and soc_therm clock frequencies for the
upcoming soctherm driver.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
parent cb44cc2f

drivers/clk/tegra/clk-tegra124.c

+6 −0
Original line number Diff line number Diff line
@@ -1371,6 +1371,12 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0},

	{TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},

	{TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},

	{TEGRA124_CLK_EMC, TEGRA124_CLK_CLK_MAX, 0, 1},

	{TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},

	{TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},

	{TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},

	{TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},

	{TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},

	/* This MUST be the last entry. */

	{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},

};