Loading drivers/gpu/drm/msm/dp/dp_aux.c +1 −10 Original line number Diff line number Diff line Loading @@ -371,11 +371,8 @@ static void dp_aux_transfer_helper(struct dp_aux_private *aux, bool i2c_read = input_msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ); if (!i2c_mot || !i2c_read || (input_msg->size == 0)) { /* reset the offset for all other transaction types */ aux->offset = 0; if (!i2c_mot || !i2c_read || (input_msg->size == 0)) return; } /* * Sending the segment value and EDID offset will be performed Loading Loading @@ -498,12 +495,6 @@ static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux, goto address_error; } if ((msg->size + aux->offset) > SZ_256) { pr_err("invalid edid access: offset=0x%x, size=0x%x\n", aux->offset, msg->size); goto address_error; } if (aux->native) { if (aux->read) { aux->dp_aux.reg = msg->address; Loading drivers/gpu/drm/msm/dp/dp_ctrl.c +23 −17 Original line number Diff line number Diff line Loading @@ -147,7 +147,7 @@ static void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl, enum dp_stream_id strm) if (!wait_for_completion_timeout(&ctrl->idle_comp, idle_pattern_completion_timeout_ms)) pr_warn("PUSH_IDLE pattern timedout\n"); pr_warn("PUSH_IDLE time out\n"); pr_debug("mainlink off done\n"); } Loading Loading @@ -179,11 +179,11 @@ static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) ret = wait_for_completion_timeout(&ctrl->video_comp, HZ / 2); if (ret <= 0) { pr_err("Link Train timedout\n"); ret = -EINVAL; pr_err("SEND_VIDEO time out (%d)\n", ret); return -EINVAL; } return ret; return 0; } static int dp_ctrl_update_sink_vx_px(struct dp_ctrl_private *ctrl, Loading Loading @@ -838,21 +838,22 @@ static void dp_ctrl_reset(struct dp_ctrl *dp_ctrl) ctrl->catalog->reset(ctrl->catalog); } static void dp_ctrl_send_video(struct dp_ctrl_private *ctrl) { ctrl->catalog->state_ctrl(ctrl->catalog, ST_SEND_VIDEO); } static int dp_ctrl_mst_stream_setup(struct dp_ctrl_private *ctrl, struct dp_panel *panel) { u32 x_int, y_frac_enum, lanes, bw_code; bool act_complete; if (!ctrl->mst_mode) { ctrl->catalog->state_ctrl(ctrl->catalog, ST_SEND_VIDEO); if (!ctrl->mst_mode) return 0; } DP_MST_DEBUG("mst stream channel allocation\n"); panel->hw_cfg(panel); ctrl->catalog->channel_alloc(ctrl->catalog, panel->stream_id, panel->channel_start_slot, Loading @@ -875,8 +876,6 @@ static int dp_ctrl_mst_stream_setup(struct dp_ctrl_private *ctrl, DP_MST_DEBUG("mst lane_cnt:%d, bw:%d, x_int:%d, y_frac:%d\n", lanes, bw_code, x_int, y_frac_enum); ctrl->catalog->state_ctrl(ctrl->catalog, ST_SEND_VIDEO); ctrl->catalog->trigger_act(ctrl->catalog); msleep(20); /* needs 1 frame time */ Loading @@ -897,8 +896,7 @@ static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel) struct dp_ctrl_private *ctrl; if (!dp_ctrl || !panel) { rc = -EINVAL; goto end; return -EINVAL; } ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); Loading @@ -906,7 +904,7 @@ static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel) rc = dp_ctrl_enable_stream_clocks(ctrl, panel); if (rc) { pr_err("failure on stream clock enable\n"); goto end; return rc; } if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { Loading @@ -914,15 +912,23 @@ static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel) return 0; } rc = panel->hw_cfg(panel); if (rc) return rc; dp_ctrl_send_video(ctrl); rc = dp_ctrl_mst_stream_setup(ctrl, panel); if (rc) goto end; return rc; rc = dp_ctrl_wait4video_ready(ctrl); if (rc) return rc; dp_ctrl_wait4video_ready(ctrl); link_ready = ctrl->catalog->mainlink_ready(ctrl->catalog); pr_debug("mainlink %s\n", link_ready ? "READY" : "NOT READY"); end: return rc; } Loading drivers/gpu/drm/msm/dp/dp_debug.c +80 −0 Original line number Diff line number Diff line Loading @@ -399,6 +399,72 @@ static ssize_t dp_debug_mst_mode_write(struct file *file, return len; } static ssize_t dp_debug_max_pclk_khz_write(struct file *file, const char __user *user_buff, size_t count, loff_t *ppos) { struct dp_debug_private *debug = file->private_data; char buf[SZ_8]; size_t len = 0; u32 max_pclk = 0; if (!debug) return -ENODEV; if (*ppos) return 0; len = min_t(size_t, count, SZ_8 - 1); if (copy_from_user(buf, user_buff, len)) return 0; buf[len] = '\0'; if (kstrtoint(buf, 10, &max_pclk) != 0) return 0; if (max_pclk > debug->parser->max_pclk_khz) pr_err("requested: %d, max_pclk_khz:%d\n", max_pclk, debug->parser->max_pclk_khz); else debug->dp_debug.max_pclk_khz = max_pclk; pr_debug("max_pclk_khz: %d\n", max_pclk); return len; } static ssize_t dp_debug_max_pclk_khz_read(struct file *file, char __user *user_buff, size_t count, loff_t *ppos) { struct dp_debug_private *debug = file->private_data; char *buf; u32 len = 0; if (!debug) return -ENODEV; if (*ppos) return 0; buf = kzalloc(SZ_4K, GFP_KERNEL); if (!buf) return -ENOMEM; len += snprintf(buf + len, (SZ_4K - len), "max_pclk_khz = %d, org: %d\n", debug->dp_debug.max_pclk_khz, debug->parser->max_pclk_khz); if (copy_to_user(user_buff, buf, len)) { kfree(buf); return -EFAULT; } *ppos += len; kfree(buf); return len; } static ssize_t dp_debug_mst_sideband_mode_write(struct file *file, const char __user *user_buff, size_t count, loff_t *ppos) { Loading Loading @@ -1154,6 +1220,12 @@ static const struct file_operations mst_sideband_mode_fops = { .write = dp_debug_mst_sideband_mode_write, }; static const struct file_operations max_pclk_khz_fops = { .open = simple_open, .write = dp_debug_max_pclk_khz_write, .read = dp_debug_max_pclk_khz_read, }; static int dp_debug_init(struct dp_debug *dp_debug) { int rc = 0; Loading Loading @@ -1309,6 +1381,14 @@ static int dp_debug_init(struct dp_debug *dp_debug) DEBUG_NAME, rc); } file = debugfs_create_file("max_pclk_khz", 0644, dir, debug, &max_pclk_khz_fops); if (IS_ERR_OR_NULL(file)) { rc = PTR_ERR(file); pr_err("[%s] debugfs max_pclk_khz failed, rc=%d\n", DEBUG_NAME, rc); } return 0; error_remove_dir: Loading drivers/gpu/drm/msm/dp/dp_debug.h +2 −0 Original line number Diff line number Diff line Loading @@ -27,6 +27,7 @@ * @hdisplay: used to filter out hdisplay value * @vrefresh: used to filter out vrefresh value * @tpg_state: specifies whether tpg feature is enabled * @max_pclk_khz: max pclk supported */ struct dp_debug { bool debug_en; Loading @@ -37,6 +38,7 @@ struct dp_debug { int hdisplay; int vrefresh; bool tpg_state; u32 max_pclk_khz; u8 *(*get_edid)(struct dp_debug *dp_debug); }; Loading drivers/gpu/drm/msm/dp/dp_display.c +10 −4 Original line number Diff line number Diff line Loading @@ -564,8 +564,13 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) dp->link->process_request(dp->link); dp->panel->handle_sink_request(dp->panel); if (dp->debug->max_pclk_khz) dp->dp_display.max_pclk_khz = dp->debug->max_pclk_khz; else dp->dp_display.max_pclk_khz = dp->parser->max_pclk_khz; pr_debug("dp max_pclk_khz = %d\n", dp->dp_display.max_pclk_khz); dp_display_process_mst_hpd_high(dp); notify: dp_display_send_hpd_notification(dp, true); Loading Loading @@ -1269,7 +1274,9 @@ static int dp_display_enable(struct dp_display *dp_display, void *panel) } rc = dp->ctrl->on(dp->ctrl, dp->mst.mst_active); if (!rc) if (rc) goto end; dp->power_on = true; stream_setup: Loading @@ -1285,7 +1292,6 @@ static void dp_display_stream_post_enable(struct dp_display_private *dp, { dp_panel->spd_config(dp_panel); dp_panel->setup_hdr(dp_panel, NULL); dp_panel->hw_cfg(dp_panel); dp_panel->audio->register_ext_disp(dp_panel->audio); } Loading Loading
drivers/gpu/drm/msm/dp/dp_aux.c +1 −10 Original line number Diff line number Diff line Loading @@ -371,11 +371,8 @@ static void dp_aux_transfer_helper(struct dp_aux_private *aux, bool i2c_read = input_msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ); if (!i2c_mot || !i2c_read || (input_msg->size == 0)) { /* reset the offset for all other transaction types */ aux->offset = 0; if (!i2c_mot || !i2c_read || (input_msg->size == 0)) return; } /* * Sending the segment value and EDID offset will be performed Loading Loading @@ -498,12 +495,6 @@ static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux, goto address_error; } if ((msg->size + aux->offset) > SZ_256) { pr_err("invalid edid access: offset=0x%x, size=0x%x\n", aux->offset, msg->size); goto address_error; } if (aux->native) { if (aux->read) { aux->dp_aux.reg = msg->address; Loading
drivers/gpu/drm/msm/dp/dp_ctrl.c +23 −17 Original line number Diff line number Diff line Loading @@ -147,7 +147,7 @@ static void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl, enum dp_stream_id strm) if (!wait_for_completion_timeout(&ctrl->idle_comp, idle_pattern_completion_timeout_ms)) pr_warn("PUSH_IDLE pattern timedout\n"); pr_warn("PUSH_IDLE time out\n"); pr_debug("mainlink off done\n"); } Loading Loading @@ -179,11 +179,11 @@ static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) ret = wait_for_completion_timeout(&ctrl->video_comp, HZ / 2); if (ret <= 0) { pr_err("Link Train timedout\n"); ret = -EINVAL; pr_err("SEND_VIDEO time out (%d)\n", ret); return -EINVAL; } return ret; return 0; } static int dp_ctrl_update_sink_vx_px(struct dp_ctrl_private *ctrl, Loading Loading @@ -838,21 +838,22 @@ static void dp_ctrl_reset(struct dp_ctrl *dp_ctrl) ctrl->catalog->reset(ctrl->catalog); } static void dp_ctrl_send_video(struct dp_ctrl_private *ctrl) { ctrl->catalog->state_ctrl(ctrl->catalog, ST_SEND_VIDEO); } static int dp_ctrl_mst_stream_setup(struct dp_ctrl_private *ctrl, struct dp_panel *panel) { u32 x_int, y_frac_enum, lanes, bw_code; bool act_complete; if (!ctrl->mst_mode) { ctrl->catalog->state_ctrl(ctrl->catalog, ST_SEND_VIDEO); if (!ctrl->mst_mode) return 0; } DP_MST_DEBUG("mst stream channel allocation\n"); panel->hw_cfg(panel); ctrl->catalog->channel_alloc(ctrl->catalog, panel->stream_id, panel->channel_start_slot, Loading @@ -875,8 +876,6 @@ static int dp_ctrl_mst_stream_setup(struct dp_ctrl_private *ctrl, DP_MST_DEBUG("mst lane_cnt:%d, bw:%d, x_int:%d, y_frac:%d\n", lanes, bw_code, x_int, y_frac_enum); ctrl->catalog->state_ctrl(ctrl->catalog, ST_SEND_VIDEO); ctrl->catalog->trigger_act(ctrl->catalog); msleep(20); /* needs 1 frame time */ Loading @@ -897,8 +896,7 @@ static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel) struct dp_ctrl_private *ctrl; if (!dp_ctrl || !panel) { rc = -EINVAL; goto end; return -EINVAL; } ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); Loading @@ -906,7 +904,7 @@ static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel) rc = dp_ctrl_enable_stream_clocks(ctrl, panel); if (rc) { pr_err("failure on stream clock enable\n"); goto end; return rc; } if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { Loading @@ -914,15 +912,23 @@ static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel) return 0; } rc = panel->hw_cfg(panel); if (rc) return rc; dp_ctrl_send_video(ctrl); rc = dp_ctrl_mst_stream_setup(ctrl, panel); if (rc) goto end; return rc; rc = dp_ctrl_wait4video_ready(ctrl); if (rc) return rc; dp_ctrl_wait4video_ready(ctrl); link_ready = ctrl->catalog->mainlink_ready(ctrl->catalog); pr_debug("mainlink %s\n", link_ready ? "READY" : "NOT READY"); end: return rc; } Loading
drivers/gpu/drm/msm/dp/dp_debug.c +80 −0 Original line number Diff line number Diff line Loading @@ -399,6 +399,72 @@ static ssize_t dp_debug_mst_mode_write(struct file *file, return len; } static ssize_t dp_debug_max_pclk_khz_write(struct file *file, const char __user *user_buff, size_t count, loff_t *ppos) { struct dp_debug_private *debug = file->private_data; char buf[SZ_8]; size_t len = 0; u32 max_pclk = 0; if (!debug) return -ENODEV; if (*ppos) return 0; len = min_t(size_t, count, SZ_8 - 1); if (copy_from_user(buf, user_buff, len)) return 0; buf[len] = '\0'; if (kstrtoint(buf, 10, &max_pclk) != 0) return 0; if (max_pclk > debug->parser->max_pclk_khz) pr_err("requested: %d, max_pclk_khz:%d\n", max_pclk, debug->parser->max_pclk_khz); else debug->dp_debug.max_pclk_khz = max_pclk; pr_debug("max_pclk_khz: %d\n", max_pclk); return len; } static ssize_t dp_debug_max_pclk_khz_read(struct file *file, char __user *user_buff, size_t count, loff_t *ppos) { struct dp_debug_private *debug = file->private_data; char *buf; u32 len = 0; if (!debug) return -ENODEV; if (*ppos) return 0; buf = kzalloc(SZ_4K, GFP_KERNEL); if (!buf) return -ENOMEM; len += snprintf(buf + len, (SZ_4K - len), "max_pclk_khz = %d, org: %d\n", debug->dp_debug.max_pclk_khz, debug->parser->max_pclk_khz); if (copy_to_user(user_buff, buf, len)) { kfree(buf); return -EFAULT; } *ppos += len; kfree(buf); return len; } static ssize_t dp_debug_mst_sideband_mode_write(struct file *file, const char __user *user_buff, size_t count, loff_t *ppos) { Loading Loading @@ -1154,6 +1220,12 @@ static const struct file_operations mst_sideband_mode_fops = { .write = dp_debug_mst_sideband_mode_write, }; static const struct file_operations max_pclk_khz_fops = { .open = simple_open, .write = dp_debug_max_pclk_khz_write, .read = dp_debug_max_pclk_khz_read, }; static int dp_debug_init(struct dp_debug *dp_debug) { int rc = 0; Loading Loading @@ -1309,6 +1381,14 @@ static int dp_debug_init(struct dp_debug *dp_debug) DEBUG_NAME, rc); } file = debugfs_create_file("max_pclk_khz", 0644, dir, debug, &max_pclk_khz_fops); if (IS_ERR_OR_NULL(file)) { rc = PTR_ERR(file); pr_err("[%s] debugfs max_pclk_khz failed, rc=%d\n", DEBUG_NAME, rc); } return 0; error_remove_dir: Loading
drivers/gpu/drm/msm/dp/dp_debug.h +2 −0 Original line number Diff line number Diff line Loading @@ -27,6 +27,7 @@ * @hdisplay: used to filter out hdisplay value * @vrefresh: used to filter out vrefresh value * @tpg_state: specifies whether tpg feature is enabled * @max_pclk_khz: max pclk supported */ struct dp_debug { bool debug_en; Loading @@ -37,6 +38,7 @@ struct dp_debug { int hdisplay; int vrefresh; bool tpg_state; u32 max_pclk_khz; u8 *(*get_edid)(struct dp_debug *dp_debug); }; Loading
drivers/gpu/drm/msm/dp/dp_display.c +10 −4 Original line number Diff line number Diff line Loading @@ -564,8 +564,13 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) dp->link->process_request(dp->link); dp->panel->handle_sink_request(dp->panel); if (dp->debug->max_pclk_khz) dp->dp_display.max_pclk_khz = dp->debug->max_pclk_khz; else dp->dp_display.max_pclk_khz = dp->parser->max_pclk_khz; pr_debug("dp max_pclk_khz = %d\n", dp->dp_display.max_pclk_khz); dp_display_process_mst_hpd_high(dp); notify: dp_display_send_hpd_notification(dp, true); Loading Loading @@ -1269,7 +1274,9 @@ static int dp_display_enable(struct dp_display *dp_display, void *panel) } rc = dp->ctrl->on(dp->ctrl, dp->mst.mst_active); if (!rc) if (rc) goto end; dp->power_on = true; stream_setup: Loading @@ -1285,7 +1292,6 @@ static void dp_display_stream_post_enable(struct dp_display_private *dp, { dp_panel->spd_config(dp_panel); dp_panel->setup_hdr(dp_panel, NULL); dp_panel->hw_cfg(dp_panel); dp_panel->audio->register_ext_disp(dp_panel->audio); } Loading