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Commit 0a625fd2 authored by David S. Miller's avatar David S. Miller Committed by Herbert Xu
Browse files

crypto: n2 - Add Niagara2 crypto driver 



Current deficiencies:

1) No HMAC hash support yet.

2) Although the algs are registered as ASYNC they always run
   synchronously.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent bf06099d

drivers/crypto/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -170,6 +170,18 @@ config CRYPTO_DEV_MV_CESA 


	  Currently the driver supports AES in ECB and CBC mode without DMA.



config CRYPTO_DEV_NIAGARA2

       tristate "Niagara2 Stream Processing Unit driver"

       select CRYPTO_ALGAPI

       depends on SPARC64

       help

	  Each core of a Niagara2 processor contains a Stream

	  Processing Unit, which itself contains several cryptographic

	  sub-units.  One set provides the Modular Arithmetic Unit,

	  used for SSL offload.  The other set provides the Cipher

	  Group, which can perform encryption, decryption, hashing,

	  checksumming, and raw copies.



config CRYPTO_DEV_HIFN_795X

	tristate "Driver HIFN 795x crypto accelerator chips"

	select CRYPTO_DES

drivers/crypto/Makefile

+2 −0
Original line number Diff line number Diff line 
obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) += padlock-aes.o

obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += padlock-sha.o

obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o

obj-$(CONFIG_CRYPTO_DEV_NIAGARA2) += n2_crypto.o

n2_crypto-objs := n2_core.o n2_asm.o

obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o

obj-$(CONFIG_CRYPTO_DEV_MV_CESA) += mv_cesa.o

obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o

drivers/crypto/n2_asm.S

0 → 100644
+95 −0
Original line number Diff line number Diff line 
/* n2_asm.S: Hypervisor calls for NCS support.

 *

 * Copyright (C) 2009 David S. Miller <davem@davemloft.net>

 */



#include <linux/linkage.h>

#include <asm/hypervisor.h>

#include "n2_core.h"



	/* o0: queue type

	 * o1: RA of queue

	 * o2: num entries in queue

	 * o3: address of queue handle return

	 */

ENTRY(sun4v_ncs_qconf)

	mov	HV_FAST_NCS_QCONF, %o5

	ta	HV_FAST_TRAP

	stx	%o1, [%o3]

	retl

	 nop

ENDPROC(sun4v_ncs_qconf)



	/* %o0: queue handle

	 * %o1: address of queue type return

	 * %o2: address of queue base address return

	 * %o3: address of queue num entries return

	 */

ENTRY(sun4v_ncs_qinfo)

	mov	%o1, %g1

	mov	%o2, %g2

	mov	%o3, %g3

	mov	HV_FAST_NCS_QINFO, %o5

	ta	HV_FAST_TRAP

	stx	%o1, [%g1]

	stx	%o2, [%g2]

	stx	%o3, [%g3]

	retl

	 nop

ENDPROC(sun4v_ncs_qinfo)



	/* %o0: queue handle

	 * %o1: address of head offset return

	 */

ENTRY(sun4v_ncs_gethead)

	mov	%o1, %o2

	mov	HV_FAST_NCS_GETHEAD, %o5

	ta	HV_FAST_TRAP

	stx	%o1, [%o2]

	retl

	 nop

ENDPROC(sun4v_ncs_gethead)



	/* %o0: queue handle

	 * %o1: address of tail offset return

	 */

ENTRY(sun4v_ncs_gettail)

	mov	%o1, %o2

	mov	HV_FAST_NCS_GETTAIL, %o5

	ta	HV_FAST_TRAP

	stx	%o1, [%o2]

	retl

	 nop

ENDPROC(sun4v_ncs_gettail)



	/* %o0: queue handle

	 * %o1: new tail offset

	 */

ENTRY(sun4v_ncs_settail)

	mov	HV_FAST_NCS_SETTAIL, %o5

	ta	HV_FAST_TRAP

	retl

	 nop

ENDPROC(sun4v_ncs_settail)



	/* %o0: queue handle

	 * %o1: address of devino return

	 */

ENTRY(sun4v_ncs_qhandle_to_devino)

	mov	%o1, %o2

	mov	HV_FAST_NCS_QHANDLE_TO_DEVINO, %o5

	ta	HV_FAST_TRAP

	stx	%o1, [%o2]

	retl

	 nop

ENDPROC(sun4v_ncs_qhandle_to_devino)



	/* %o0: queue handle

	 * %o1: new head offset

	 */

ENTRY(sun4v_ncs_sethead_marker)

	mov	HV_FAST_NCS_SETHEAD_MARKER, %o5

	ta	HV_FAST_TRAP

	retl

	 nop

ENDPROC(sun4v_ncs_sethead_marker)