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Commit 0a07232f authored by Krzysztof Hałasa's avatar Krzysztof Hałasa
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IXP4xx: workaround for PCI prefetch problems near 64 MB boundary. 



Map unused registers at the end of DMA region at 64 MB to allow PCI masters
to cross the boundary when prefetching data from SDRAM.

Signed-off-by: default avatarKrzysztof Hałasa <khc@pm.waw.pl>
parent fec6c6fe

arch/arm/include/asm/sizes.h

+1 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 
#define SZ_8M                           0x00800000

#define SZ_16M                          0x01000000

#define SZ_32M                          0x02000000

#define SZ_48M                          0x03000000

#define SZ_64M                          0x04000000

#define SZ_128M                         0x08000000

#define SZ_256M                         0x10000000

arch/arm/mach-ixp4xx/common-pci.c

+12 −11
Original line number Diff line number Diff line
@@ -411,15 +411,16 @@ void __init ixp4xx_pci_preinit(void) 
		 * We configure the PCI inbound memory windows to be

		 * 1:1 mapped to SDRAM

		 */

		local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000);

		local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000);

		local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000);

		local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000);

		local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);

		local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);

		local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);

		local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M);



		/*

		 * Enable CSR window at 0xff000000.

		 * Enable CSR window at 64 MiB to allow PCI masters

		 * to continue prefetching past 64 MiB boundary.

		 */

		local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008);

		local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);



		/*

		 * Enable the IO window to be way up high, at 0xfffffc00