Merge "ARM: dts: msm: Add L1 cache definitions to sdm855" into msm-next (096d54a8) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sdm855.dtsi

+164 −0

Original line number	Diff line number	Diff line
		@@ -58,6 +58,16 @@
		cache-level = <3>;
		};
		};

		L1_I_0: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0xa000>;
		};

		L1_D_0: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0xa000>;
		};
		};

		CPU1: cpu@100 {
		@@ -73,6 +83,16 @@
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		};

		L1_I_100: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0xa000>;
		};

		L1_D_100: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0xa000>;
		};
		};

		CPU2: cpu@200 {
		@@ -88,6 +108,16 @@
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		};

		L1_I_200: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0xa000>;
		};

		L1_D_200: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0xa000>;
		};
		};

		CPU3: cpu@300 {
		@@ -103,6 +133,16 @@
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		};

		L1_I_300: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0xa000>;
		};

		L1_D_300: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0xa000>;
		};
		};

		CPU4: cpu@400 {
		@@ -118,6 +158,16 @@
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		};

		L1_I_400: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x14000>;
		};

		L1_D_400: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x14000>;
		};
		};

		CPU5: cpu@500 {
		@@ -133,6 +183,16 @@
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		};

		L1_I_500: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x14000>;
		};

		L1_D_500: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x14000>;
		};
		};

		CPU6: cpu@600 {
		@@ -148,6 +208,16 @@
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		};

		L1_I_600: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x14000>;
		};

		L1_D_600: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x14000>;
		};
		};

		CPU7: cpu@700 {
		@@ -163,6 +233,16 @@
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		};

		L1_I_700: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x14000>;
		};

		L1_D_700: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x14000>;
		};
		};

		cpu-map {
		@@ -818,6 +898,90 @@
		};
		};

		cpuss_dump {
		compatible = "qcom,cpuss-dump";

		qcom,l1_i_cache0 {
		qcom,dump-node = <&L1_I_0>;
		qcom,dump-id = <0x60>;
		};

		qcom,l1_i_cache1 {
		qcom,dump-node = <&L1_I_100>;
		qcom,dump-id = <0x61>;
		};

		qcom,l1_i_cache2 {
		qcom,dump-node = <&L1_I_200>;
		qcom,dump-id = <0x62>;
		};

		qcom,l1_i_cache3 {
		qcom,dump-node = <&L1_I_300>;
		qcom,dump-id = <0x63>;
		};

		qcom,l1_i_cache100 {
		qcom,dump-node = <&L1_I_400>;
		qcom,dump-id = <0x64>;
		};

		qcom,l1_i_cache101 {
		qcom,dump-node = <&L1_I_500>;
		qcom,dump-id = <0x65>;
		};

		qcom,l1_i_cache102 {
		qcom,dump-node = <&L1_I_600>;
		qcom,dump-id = <0x66>;
		};

		qcom,l1_i_cache103 {
		qcom,dump-node = <&L1_I_700>;
		qcom,dump-id = <0x67>;
		};

		qcom,l1_d_cache0 {
		qcom,dump-node = <&L1_D_0>;
		qcom,dump-id = <0x80>;
		};

		qcom,l1_d_cache1 {
		qcom,dump-node = <&L1_D_100>;
		qcom,dump-id = <0x81>;
		};

		qcom,l1_d_cache2 {
		qcom,dump-node = <&L1_D_200>;
		qcom,dump-id = <0x82>;
		};

		qcom,l1_d_cache3 {
		qcom,dump-node = <&L1_D_300>;
		qcom,dump-id = <0x83>;
		};

		qcom,l1_d_cache100 {
		qcom,dump-node = <&L1_D_400>;
		qcom,dump-id = <0x84>;
		};

		qcom,l1_d_cache101 {
		qcom,dump-node = <&L1_D_500>;
		qcom,dump-id = <0x85>;
		};

		qcom,l1_d_cache102 {
		qcom,dump-node = <&L1_D_600>;
		qcom,dump-id = <0x86>;
		};

		qcom,l1_d_cache103 {
		qcom,dump-node = <&L1_D_700>;
		qcom,dump-id = <0x87>;
		};
		};

		usb0: ssusb@a600000 {
		compatible = "qcom,dwc3";
		reg = <0x0a600000 0x100000>;