Commit 095c0669 authored Mar 27, 2019 by Akhil P Oommen

msm: kgsl: Avoid register write miss for a fenced register

In adreno_gmu_fenced_write(), it is possible that the register write
is posted after reading the fence status register, which in this case
will return a Success. But the register write may be dropped. We can
avoid this by forcing the order of the read/write operations with a
barrier. Put a memory barrier after the register write to make sure
the write is posted before the register is read.

Change-Id: I7882c3e9d1f7e5182fedafe0b28727f777c7bd7f
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>

parent 5395b739

drivers/gpu/msm/adreno.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -3379,6 +3379,12 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,
		return 0;

		for (i = 0; i < GMU_CORE_LONG_WAKEUP_RETRY_LIMIT; i++) {
		/*
		* Make sure the previous register write is posted before
		* checking the fence status
		*/
		mb();

		adreno_read_gmureg(adreno_dev, ADRENO_REG_GMU_AHB_FENCE_STATUS,
		&status);