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Commit 089d0362 authored by Daniel Mack's avatar Daniel Mack Committed by Haojian Zhuang
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ARM: pxa: add devicetree code for irq handling 



Properly register on-chip interrupt using the irqdomain logic. The
number of interrupts is taken from the devicetree node. That includes
the following changes:

- cpu_has_ipr() was converted from an inline function to a static bool
variable, so it can be set using the "marvell,intc-priority" property
inside the device node of the tree.

- IRQ_BASE was converted from a macro to a runtime variable so that it
can be initialized dynamically from the DT init code.

- irq_base() now uses pxa_irq_base and just adds an offset.

Hence, there are now no compile-time fixed values used in case of DT
initialization.

Signed-off-by: default avatarDaniel Mack <zonque@gmail.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@gmail.com>
parent 9450be76

arch/arm/mach-pxa/irq.c

+110 −21
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ 
#include <linux/syscore_ops.h>

#include <linux/io.h>

#include <linux/irq.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>



#include <asm/exception.h>
@@ -25,8 +27,6 @@ 


#include "generic.h"



#define IRQ_BASE		io_p2v(0x40d00000)



#define ICIP			(0x000)

#define ICMR			(0x004)

#define ICLR			(0x008)
@@ -48,22 +48,19 @@ 
 * This is for peripheral IRQs internal to the PXA chip.

 */



static void __iomem *pxa_irq_base;

static int pxa_internal_irq_nr;



static inline int cpu_has_ipr(void)

{

	return !cpu_is_pxa25x();

}

static bool cpu_has_ipr;



static inline void __iomem *irq_base(int i)

{

	static unsigned long phys_base[] = {

		0x40d00000,

		0x40d0009c,

		0x40d00130,

	static unsigned long phys_base_offset[] = {

		0x0,

		0x9c,

		0x130,

	};



	return io_p2v(phys_base[i]);

	return pxa_irq_base + phys_base_offset[i];

}



void pxa_mask_irq(struct irq_data *d)
@@ -96,8 +93,8 @@ asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) 
	uint32_t icip, icmr, mask;



	do {

		icip = __raw_readl(IRQ_BASE + ICIP);

		icmr = __raw_readl(IRQ_BASE + ICMR);

		icip = __raw_readl(pxa_irq_base + ICIP);

		icmr = __raw_readl(pxa_irq_base + ICMR);

		mask = icip & icmr;



		if (mask == 0)
@@ -128,6 +125,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) 
	BUG_ON(irq_nr > MAX_INTERNAL_IRQS);



	pxa_internal_irq_nr = irq_nr;

	cpu_has_ipr = !cpu_is_pxa25x();

	pxa_irq_base = io_p2v(0x40d00000);



	for (n = 0; n < irq_nr; n += 32) {

		void __iomem *base = irq_base(n >> 5);
@@ -136,8 +135,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) 
		__raw_writel(0, base + ICLR);	/* all IRQs are IRQ, not FIQ */

		for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {

			/* initialize interrupt priority */

			if (cpu_has_ipr())

				__raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));

			if (cpu_has_ipr)

				__raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));



			irq = PXA_IRQ(i);

			irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
@@ -168,9 +167,9 @@ static int pxa_irq_suspend(void) 
		__raw_writel(0, base + ICMR);

	}



	if (cpu_has_ipr()) {

	if (cpu_has_ipr) {

		for (i = 0; i < pxa_internal_irq_nr; i++)

			saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));

			saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));

	}



	return 0;
@@ -187,11 +186,11 @@ static void pxa_irq_resume(void) 
		__raw_writel(0, base + ICLR);

	}



	if (cpu_has_ipr())

	if (cpu_has_ipr)

		for (i = 0; i < pxa_internal_irq_nr; i++)

			__raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));

			__raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));



	__raw_writel(1, IRQ_BASE + ICCR);

	__raw_writel(1, pxa_irq_base + ICCR);

}

#else

#define pxa_irq_suspend		NULL
@@ -202,3 +201,93 @@ struct syscore_ops pxa_irq_syscore_ops = { 
	.suspend	= pxa_irq_suspend,

	.resume		= pxa_irq_resume,

};



#ifdef CONFIG_OF

static struct irq_domain *pxa_irq_domain;



static int pxa_irq_map(struct irq_domain *h, unsigned int virq,

		       irq_hw_number_t hw)

{

	void __iomem *base = irq_base(hw / 32);



	/* initialize interrupt priority */

	if (cpu_has_ipr)

		__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));



	irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,

				 handle_level_irq);

	irq_set_chip_data(hw, base);

	set_irq_flags(hw, IRQF_VALID);



	return 0;

}



static struct irq_domain_ops pxa_irq_ops = {

	.map    = pxa_irq_map,

	.xlate  = irq_domain_xlate_onecell,

};



static const struct of_device_id intc_ids[] __initconst = {

	{ .compatible = "marvell,pxa-intc", },

	{}

};



void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))

{

	struct device_node *node;

	const struct of_device_id *of_id;

	struct pxa_intc_conf *conf;

	struct resource res;

	int n, ret;



	node = of_find_matching_node(NULL, intc_ids);

	if (!node) {

		pr_err("Failed to find interrupt controller in arch-pxa\n");

		return;

	}

	of_id = of_match_node(intc_ids, node);

	conf = of_id->data;



	ret = of_property_read_u32(node, "marvell,intc-nr-irqs",

				   &pxa_internal_irq_nr);

	if (ret) {

		pr_err("Not found marvell,intc-nr-irqs property\n");

		return;

	}



	ret = of_address_to_resource(node, 0, &res);

	if (ret < 0) {

		pr_err("No registers defined for node\n");

		return;

	}

	pxa_irq_base = io_p2v(res.start);



	if (of_find_property(node, "marvell,intc-priority", NULL))

		cpu_has_ipr = 1;



	ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);

	if (ret < 0) {

		pr_err("Failed to allocate IRQ numbers\n");

		return;

	}



	pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,

					       &pxa_irq_ops, NULL);

	if (!pxa_irq_domain)

		panic("Unable to add PXA IRQ domain\n");



	irq_set_default_host(pxa_irq_domain);



	for (n = 0; n < pxa_internal_irq_nr; n += 32) {

		void __iomem *base = irq_base(n >> 5);



		__raw_writel(0, base + ICMR);	/* disable all IRQs */

		__raw_writel(0, base + ICLR);	/* all IRQs are IRQ, not FIQ */

	}



	/* only unmasked interrupts kick us out of idle */

	__raw_writel(1, irq_base(0) + ICCR);



	pxa_internal_irq_chip.irq_set_wake = fn;

}

#endif /* CONFIG_OF */

arch/arm/mach-pxa/pxa3xx.c

+15 −2
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ 
#define PECR_IE(n)	((1 << ((n) * 2)) << 28)

#define PECR_IS(n)	((1 << ((n) * 2)) << 29)



extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));



static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);

static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);

static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
@@ -382,7 +384,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, 
	pxa_ext_wakeup_chip.irq_set_wake = fn;

}



void __init pxa3xx_init_irq(void)

static void __init __pxa3xx_init_irq(void)

{

	/* enable CP6 access */

	u32 value;
@@ -390,10 +392,21 @@ void __init pxa3xx_init_irq(void) 
	value |= (1 << 6);

	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));



	pxa_init_irq(56, pxa3xx_set_wake);

	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);

}



void __init pxa3xx_init_irq(void)

{

	__pxa3xx_init_irq();

	pxa_init_irq(56, pxa3xx_set_wake);

}



void __init pxa3xx_dt_init_irq(void)

{

	__pxa3xx_init_irq();

	pxa_dt_irq_init(pxa3xx_set_wake);

}



static struct map_desc pxa3xx_io_desc[] __initdata = {

	{	/* Mem Ctl */

		.virtual	= (unsigned long)SMEMC_VIRT,