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Commit 089ca2b9 authored by Sumeet Sahu's avatar Sumeet Sahu Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Enable NVMe device support 



Enable dt property to use SMMU configuration
in NVMe driver.

Change-Id: Iddbf4c204fbf6c5cabbca09cc6d4f878dbb92954
Signed-off-by: default avatarSumeet Sahu <sumesahu@codeaurora.org>
parent 4c16f4bd

Documentation/devicetree/bindings/nvme/qcom,nvme.txt

0 → 100644
+50 −0
Original line number Diff line number Diff line 
= NVME(Non Volatile Memory Express) Device Tree Bindings =



Required properties:



- compatible : Must be "qcom,nvme"



If SMMU is present, also use:



- qcom,smmu : if present, SMMU attach is performed

- qcom,smmu-iova-base : SMMU IOVA start address the device can access

- qcom,smmu-iova-size : SMMU IOVA size the device can access



Optional Properties:



- qcom,smmu-attr-s1-bypass : Bypasses SMMU S1 translation

- qcom,smmu-attr-fastmap : Enables SMMU fastmap

- qcom,smmu-attr-atomic : Enables DMA alloc using GFP_ATOMIC

- qcom,smmu-attr-pt-coherent : Use if DMA coherency is available for SMMU page tables





Example:



&pcie_rc0 {



	nvme_x1: qcom,nvme@pcie_rc0 {

		compatible = "qcom,nvme";



		qcom,smmu;

		qcom,smmu-iova-base = /bits/ 64 <0x0>;

		qcom,smmu-iova-size = /bits/ 64 <0x100000000>;



		qcom,smmu-attr-s1-bypass;

	};

};



&pcie_rc1 {



	nvme_x4: qcom,nvme@pcie_rc1 {

		compatible = "qcom,nvme";



		qcom,smmu;

		qcom,smmu-iova-base = /bits/ 64 <0x0>;

		qcom,smmu-iova-size = /bits/ 64 <0x100000000>;



		qcom,smmu-attr-atomic;

		qcom,smmu-attr-fastmap;

		qcom,smmu-attr-pt-coherent;

	};

};

arch/arm64/boot/dts/qcom/sa8155-adp-alcor.dtsi

+34 −0
Original line number Diff line number Diff line
@@ -57,6 +57,40 @@ 
	};

};



&pcie_rc1 {

	nvme_x8: qcom,nvme@pcie_rc1 {

		reg = <0 0 0 0 0>;

		compatible = "qcom,nvme";

		pci-ids =

			"8086:0953",

			"8086:0a54",

			"8086:0a55",

			"8086:f1a5",

			"8086:f1a5",

			"1c58:0003",

			"1c58:0023",

			"1c5c:1327",

			"1c5f:0540",

			"144d:a821",

			"144d:a822",

			"144d:a808",

			"1d1d:1f1f",

			"1d1d:2807",

			"1d1d:2601",

			"106b:2001",

			"106b:2003",

			"1179:0115",

			"1179:0116";



		qcom,smmu;

		qcom,smmu-iova-base = /bits/ 64 <0x20000000>;

		qcom,smmu-iova-size = /bits/ 64 <0x40000000>;



		qcom,smmu-attr-atomic;

		qcom,smmu-attr-s1-bypass;

	};

};



&qupv3_se10_i2c {

	asm330@6a {

		qcom,use_qtimer = <1>; /* 0:Disable 1:Enable */