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Commit 087210cf authored by Srinivas Ramana's avatar Srinivas Ramana Committed by Gerrit - the friendly Code Review server
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arch: arm64: Add midr values for kryo2xx big cores 



Add midr value for kryo2xx big cores to apply errata workarounds for
branch prediction hardening.

Change-Id: I7ca9cfa3e6b48d5af78a5297cb76ebe6f52e519e
Signed-off-by: default avatarSrinivas Ramana <sramana@codeaurora.org>
[gkohli@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: default avatarGaurav Kohli <gkohli@codeaurora.org>
parent 26f05358

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -128,6 +128,8 @@ 
#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)

#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)

#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)

#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_KRYO2XX_GOLD \

	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD)





#ifndef __ASSEMBLY__

#ifndef __ASSEMBLY__

arch/arm64/kernel/cpu_errata.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -589,6 +589,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
			   MIDR_CPU_VAR_REV(13, 14)),

			   MIDR_CPU_VAR_REV(13, 14)),

		.enable = enable_smccc_arch_workaround_1,

		.enable = enable_smccc_arch_workaround_1,

	},

	},

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		MIDR_ALL_VERSIONS(MIDR_KRYO2XX_GOLD),

		.enable = enable_smccc_arch_workaround_1,

	},

#endif

#endif

#ifdef CONFIG_ARM64_SSBD

#ifdef CONFIG_ARM64_SSBD

	{

	{