[ARM] mm: enable sparsemem on clps7500 and RiscPC

	select TIMER_ACORN

	select ISA

	select NO_IOPORT

	select ARCH_SPARSEMEM_ENABLE

	help

	  Support for the Cirrus Logic PS7500FE system-on-a-chip.

	select HAVE_PATA_PLATFORM

	select ISA_DMA_API

	select NO_IOPORT

	select ARCH_SPARSEMEM_ENABLE

	help

	  On the Acorn Risc-PC, Linux can support the internal IDE disk and

	  CD-ROM interface, serial and parallel port, and the floppy drive.

#include <asm/memory.h>

#define MAX_PHYSADDR_BITS	32

#define MAX_PHYSMEM_BITS	32

#define SECTION_SIZE_BITS	NODE_MEM_SIZE_BITS

/*

 * Two definitions are required for sparsemem:

 *

 * MAX_PHYSMEM_BITS: The number of physical address bits required

 *   to address the last byte of memory.

 *

 * SECTION_SIZE_BITS: The number of physical address bits to cover

 *   the maximum amount of memory in a section.

 *

 * Eg, if you have 2 banks of up to 64MB at 0x80000000, 0x84000000,

 * then MAX_PHYSMEM_BITS is 32, SECTION_SIZE_BITS is 26.

 *

 * Define these in your mach/memory.h.

 */

#if !defined(SECTION_SIZE_BITS) || !defined(MAX_PHYSMEM_BITS)

#error Sparsemem is not supported on this platform

#endif

#endif

#define FLUSH_BASE_PHYS		0x00000000

#define FLUSH_BASE		0xdf000000

/*

 * Sparsemem support.  Each section is a maximum of 64MB.  The sections

 * are offset by 128MB and can cover 128MB, so that gives us a maximum

 * of 29 physmem bits.

 */

#define MAX_PHYSMEM_BITS	29

#define SECTION_SIZE_BITS	26

#endif

#define FLUSH_BASE_PHYS		0x00000000

#define FLUSH_BASE		0xdf000000

/*

 * Sparsemem support.  Each section is a maximum of 64MB.  The sections

 * are offset by 128MB and can cover 128MB, so that gives us a maximum

 * of 29 physmem bits.

 */

#define MAX_PHYSMEM_BITS	29

#define SECTION_SIZE_BITS	26

#endif