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Commit 0783a9bf authored by Marc Dietrich's avatar Marc Dietrich Committed by Olof Johansson
Browse files

ARM: tegra: paz00: fix wrong UART port on mini-pcie plug 



UARTC is connected to the mini-pcie port.

Signed-off-by: default avatarMarc Dietrich <marvin24@gmx.de>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 5f21f124

arch/arm/boot/dts/tegra-paz00.dts

+2 −2
Original line number Original line Diff line number Diff line
@@ -46,11 +46,11 @@ 
	};

	};





	serial@70006200 {

	serial@70006200 {

		status = "disable";

		clock-frequency = <216000000>;

	};

	};





	serial@70006300 {

	serial@70006300 {

		clock-frequency = <216000000>;

		status = "disable";

	};

	};





	serial@70006400 {

	serial@70006400 {

arch/arm/mach-tegra/board-paz00.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { 
		.uartclk	= 216000000,

		.uartclk	= 216000000,

	}, {

	}, {

		/* serial port on mini-pcie */

		/* serial port on mini-pcie */

		.membase	= IO_ADDRESS(TEGRA_UARTD_BASE),

		.membase	= IO_ADDRESS(TEGRA_UARTC_BASE),

		.mapbase	= TEGRA_UARTD_BASE,

		.mapbase	= TEGRA_UARTC_BASE,

		.irq		= INT_UARTD,

		.irq		= INT_UARTC,

		.flags		= UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,

		.flags		= UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,

		.type		= PORT_TEGRA,

		.type		= PORT_TEGRA,

		.iotype		= UPIO_MEM,

		.iotype		= UPIO_MEM,
@@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline, 
static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {

static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {

	/* name		parent		rate		enabled */

	/* name		parent		rate		enabled */

	{ "uarta",	"pll_p",	216000000,	true },

	{ "uarta",	"pll_p",	216000000,	true },

	{ "uartd",	"pll_p",	216000000,	true },

	{ "uartc",	"pll_p",	216000000,	true },





	{ "pll_p_out4",	"pll_p",	24000000,	true },

	{ "pll_p_out4",	"pll_p",	24000000,	true },

	{ "usbd",	"clk_m",	12000000,	false },

	{ "usbd",	"clk_m",	12000000,	false },