Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 06b9fb52 authored by Tingwei Zhang's avatar Tingwei Zhang
Browse files

coresight: tmc: Fix write point for ETR sg mode 



Write point of ETR could be over 4GB on device with more
than 4GB memory.  Align the write point to phys_addr_t
type to fix write point overflow issue.

Change-Id: I0cd4aca2214b090101762ccc7a0ed1534f6dff11
Signed-off-by: default avatarTingwei Zhang <tingwei@codeaurora.org>
parent e8329f96

drivers/hwtracing/coresight/coresight-tmc-etr.c

+1 −1
Original line number Diff line number Diff line
@@ -352,7 +352,7 @@ static void tmc_etr_sg_mem_reset(uint32_t *vaddr, uint32_t size) 
	tmc_etr_sg_tbl_flush(vaddr, size);

}



void tmc_etr_sg_rwp_pos(struct tmc_drvdata *drvdata, uint32_t rwp)

void tmc_etr_sg_rwp_pos(struct tmc_drvdata *drvdata, phys_addr_t rwp)

{

	uint32_t i = 0, pte_n = 0, last_pte;

	uint32_t *virt_st_tbl, *virt_pte;

drivers/hwtracing/coresight/coresight-tmc.h

+1 −1
Original line number Diff line number Diff line
@@ -271,7 +271,7 @@ int tmc_etr_bam_init(struct amba_device *adev, 
extern struct byte_cntr *byte_cntr_init(struct amba_device *adev,

					struct tmc_drvdata *drvdata);

extern const struct coresight_ops tmc_etr_cs_ops;

extern void tmc_etr_sg_rwp_pos(struct tmc_drvdata *drvdata, uint32_t rwp);

extern void tmc_etr_sg_rwp_pos(struct tmc_drvdata *drvdata, phys_addr_t rwp);



extern const struct coresight_ops tmc_etr_cs_ops;