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Commit 06a20d2d authored by Uma Shankar's avatar Uma Shankar Committed by Jani Nikula
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drm/i915: Fix PLL 8x/3 divider for MIPI video mode 



MIPI Video Mode for high res panels (requiring dual link), need a
8X/3 divider to be programmed as 0x2. Modifying the same
in this patch.

Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarVidya Srinivas <vidya.srinivas@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1486551058-22596-3-git-send-email-vidya.srinivas@intel.com
parent 645a2f6e

drivers/gpu/drm/i915/intel_dsi_pll.c

+1 −5
Original line number Original line Diff line number Diff line
@@ -416,11 +416,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, 
	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;

	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;

	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;

	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;





	/* As per bpsec program the 8/3X clock divider to the below value */

	if (dev_priv->vbt.dsi.config->is_cmd_mode)

	mipi_8by3_divider = 0x2;

	mipi_8by3_divider = 0x2;

	else

		mipi_8by3_divider = 0x3;





	tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);

	tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);

	tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);

	tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);