Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0599ebd9 authored by Amit Nischal's avatar Amit Nischal Committed by Gerrit - the friendly Code Review server
Browse files

clk: qcom: Add support for GCC_USB3_PHY_PRIM_SP0_BCR 



USB driver needs GCC_USB3_PHY_PRIM_SP0_BCR to bring USB3_PHY
out of reset so add support for the same. Also remove the unused
GCC_USB3PHY_PHY_PRIM_SP0_BCR.

Change-Id: I4a3d57ddd0a56b25b44366eb221b214f9a4baadd
Signed-off-by: default avatarAmit Nischal <anischal@codeaurora.org>
parent af372cc5

drivers/clk/qcom/gcc-sm6150.c

+1 −1
Original line number Diff line number Diff line
@@ -3424,8 +3424,8 @@ static const struct qcom_reset_map gcc_sm6150_resets[] = { 
	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },

	[GCC_UFS_PHY_BCR] = { 0x77000 },

	[GCC_USB20_SEC_BCR] = { 0xa6000 },

	[GCC_USB3_DP_PHY_PRIM_SP0_BCR] = { 0x50010 },

	[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x50008 },

	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },

};



static struct clk_dfs gcc_dfs_clocks[] = {

include/dt-bindings/clock/qcom,gcc-sm6150.h

+1 −1
Original line number Diff line number Diff line
@@ -204,7 +204,7 @@ 
#define GCC_PCIE_PHY_COM_BCR			9

#define GCC_UFS_PHY_BCR				10

#define GCC_USB20_SEC_BCR			11

#define GCC_USB3_DP_PHY_PRIM_SP0_BCR		12

#define GCC_USB3_PHY_PRIM_SP0_BCR		12

#define GCC_USB3PHY_PHY_PRIM_SP0_BCR		13



#endif