Commit 04521caa authored Nov 25, 2017 by Andre Przywara Committed by Greg Kroah-Hartman Feb 25, 2018

pinctrl: sunxi: Fix A64 UART mux value




[ Upstream commit 7c5c2c2d18d778e51fd8b899965097168306031c ]

To use pin PF4 as the RX signal of UART0, we have to write 0b011 into
the respective pin controller register.
Fix the wrong value we had in our table so far.

Fixes: 96851d39 ("drivers: pinctrl: add driver for Allwinner A64 SoC")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent b1f0445d

drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -428,7 +428,7 @@ static const struct sunxi_desc_pin a64_pins[] = {
		SUNXI_FUNCTION(0x0, "gpio_in"),
		SUNXI_FUNCTION(0x1, "gpio_out"),
		SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
		SUNXI_FUNCTION(0x4, "uart0")), /* RX */
		SUNXI_FUNCTION(0x3, "uart0")), /* RX */
		SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
		SUNXI_FUNCTION(0x0, "gpio_in"),
		SUNXI_FUNCTION(0x1, "gpio_out"),