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Commit 03279156 authored by Kyle Piefer's avatar Kyle Piefer Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Temporarily mask the watchdog upon receiving it 



Once the GMU watchdog interrupt is cleared and the handler
returns, if the device has not been reset the interrupt
will fire again. This can cause storms of GMU watchdog
interrupts that flood the system when something goes wrong.

Mask the GMU watchdog interrupt when we receive it, so that
we do not receive it again before we finish recovering. It
will be unmasked again the next time the GMU boots.

Change-Id: Ieb9090f9ed274d581f706dced683f811c66bba70
Signed-off-by: default avatarKyle Piefer <kpiefer@codeaurora.org>
parent ed1e6248

drivers/gpu/msm/kgsl_gmu.c

+8 −1
Original line number Diff line number Diff line
@@ -984,7 +984,7 @@ static irqreturn_t gmu_irq_handler(int irq, void *data) 
	struct kgsl_device *device = data;

	struct gmu_device *gmu = KGSL_GMU_DEVICE(device);

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	unsigned int status = 0;

	unsigned int mask, status = 0;



	adreno_read_gmureg(ADRENO_DEVICE(device),

			ADRENO_REG_GMU_AO_HOST_INTERRUPT_STATUS, &status);
@@ -993,6 +993,13 @@ static irqreturn_t gmu_irq_handler(int irq, void *data) 


	/* Ignore GMU_INT_RSCC_COMP and GMU_INT_DBD WAKEUP interrupts */

	if (status & GMU_INT_WDOG_BITE) {

		/* Temporarily mask the watchdog interrupt to prevent a storm */

		adreno_read_gmureg(adreno_dev,

				ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK, &mask);

		adreno_write_gmureg(adreno_dev,

				ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK,

				(mask | GMU_INT_WDOG_BITE));



		dev_err_ratelimited(&gmu->pdev->dev,

				"GMU watchdog expired interrupt received\n");

		adreno_set_gpu_fault(adreno_dev, ADRENO_GMU_FAULT);