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Commit 02d6112c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] User stack pointer randomisation
  [MIPS] Remove unused include/asm-mips/gfx.h
  [MIPS] Remove unused include/asm-mips/ds1216.h
  [MIPS] Workaround for RM7000 WAIT instruction aka erratum 38
  [MIPS] Make support for weakly ordered LL/SC a config option.
  [MIPS] Disable UserLocal runtime detection on platforms which never have it.
  [MIPS] Disable MT runtime detection on platforms which never support MT.
parents 0b1937ac 94109102

arch/mips/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -1190,8 +1190,19 @@ config SYS_HAS_CPU_RM9000 
config SYS_HAS_CPU_SB1

	bool



#

# CPU may reorder R->R, R->W, W->R, W->W

# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC

#

config WEAK_ORDERING

	bool



#

# CPU may reorder reads and writes beyond LL/SC

# CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC

#

config WEAK_REORDERING_BEYOND_LLSC

	bool

endmenu



#

arch/mips/kernel/cpu-probe.c

+25 −1
Original line number Diff line number Diff line
@@ -75,6 +75,27 @@ static void r4k_wait_irqoff(void) 
	local_irq_enable();

}



/*

 * The RM7000 variant has to handle erratum 38.  The workaround is to not

 * have any pending stores when the WAIT instruction is executed.

 */

static void rm7k_wait_irqoff(void)

{

	local_irq_disable();

	if (!need_resched())

		__asm__(

		"	.set	push					\n"

		"	.set	mips3					\n"

		"	.set	noat					\n"

		"	mfc0	$1, $12					\n"

		"	sync						\n"

		"	mtc0	$1, $12		# stalls until W stage	\n"

		"	wait						\n"

		"	mtc0	$1, $12		# stalls until W stage	\n"

		"	.set	pop					\n");

	local_irq_enable();

}



/* The Au1xxx wait is available only if using 32khz counter or

 * external timer source, but specifically not CP0 Counter. */

int allow_au1k_wait;
@@ -132,7 +153,6 @@ static inline void check_wait(void) 
	case CPU_R4700:

	case CPU_R5000:

	case CPU_NEVADA:

	case CPU_RM7000:

	case CPU_4KC:

	case CPU_4KEC:

	case CPU_4KSC:
@@ -142,6 +162,10 @@ static inline void check_wait(void) 
		cpu_wait = r4k_wait;

		break;



	case CPU_RM7000:

		cpu_wait = rm7k_wait_irqoff;

		break;



	case CPU_24K:

	case CPU_34K:

		cpu_wait = r4k_wait;

arch/mips/kernel/process.c

+14 −0
Original line number Diff line number Diff line
@@ -25,7 +25,9 @@ 
#include <linux/init.h>

#include <linux/completion.h>

#include <linux/kallsyms.h>

#include <linux/random.h>



#include <asm/asm.h>

#include <asm/bootinfo.h>

#include <asm/cpu.h>

#include <asm/dsp.h>
@@ -460,3 +462,15 @@ unsigned long get_wchan(struct task_struct *task) 
out:

	return pc;

}



/*

 * Don't forget that the stack pointer must be aligned on a 8 bytes

 * boundary for 32-bits ABI and 16 bytes for 64-bits ABI.

 */

unsigned long arch_align_stack(unsigned long sp)

{

	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)

		sp -= get_random_int() & ~PAGE_MASK;



	return sp & ALMASK;

}

include/asm-mips/atomic.h

+17 −16
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) 
{

	unsigned long result;



	smp_mb();

	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;
@@ -181,7 +181,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) 
		raw_local_irq_restore(flags);

	}



	smp_mb();

	smp_llsc_mb();



	return result;

}
@@ -190,7 +190,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) 
{

	unsigned long result;



	smp_mb();

	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;
@@ -233,7 +233,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) 
		raw_local_irq_restore(flags);

	}



	smp_mb();

	smp_llsc_mb();



	return result;

}
@@ -250,7 +250,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) 
{

	unsigned long result;



	smp_mb();

	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;
@@ -302,7 +302,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) 
		raw_local_irq_restore(flags);

	}



	smp_mb();

	smp_llsc_mb();



	return result;

}
@@ -519,7 +519,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) 
{

	unsigned long result;



	smp_mb();

	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;
@@ -562,7 +562,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) 
		raw_local_irq_restore(flags);

	}



	smp_mb();

	smp_llsc_mb();



	return result;

}
@@ -571,7 +571,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) 
{

	unsigned long result;



	smp_mb();

	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;
@@ -614,7 +614,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) 
		raw_local_irq_restore(flags);

	}



	smp_mb();

	smp_llsc_mb();



	return result;

}
@@ -631,7 +631,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) 
{

	unsigned long result;



	smp_mb();

	smp_llsc_mb();



	if (cpu_has_llsc && R10000_LLSC_WAR) {

		unsigned long temp;
@@ -683,7 +683,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) 
		raw_local_irq_restore(flags);

	}



	smp_mb();

	smp_llsc_mb();



	return result;

}
@@ -791,10 +791,11 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) 
 * atomic*_return operations are serializing but not the non-*_return

 * versions.

 */

#define smp_mb__before_atomic_dec()	smp_mb()

#define smp_mb__after_atomic_dec()	smp_mb()

#define smp_mb__before_atomic_inc()	smp_mb()

#define smp_mb__after_atomic_inc()	smp_mb()

#define smp_mb__before_atomic_dec()	smp_llsc_mb()

#define smp_mb__after_atomic_dec()	smp_llsc_mb()

#define smp_mb__before_atomic_inc()	smp_llsc_mb()

#define smp_mb__after_atomic_inc()	smp_llsc_mb()



#include <asm-generic/atomic.h>



#endif /* _ASM_ATOMIC_H */

include/asm-mips/barrier.h

+9 −0
Original line number Diff line number Diff line
@@ -121,6 +121,11 @@ 
#else

#define __WEAK_ORDERING_MB	"		\n"

#endif

#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)

#define __WEAK_LLSC_MB		"       sync	\n"

#else

#define __WEAK_LLSC_MB		"		\n"

#endif



#define smp_mb()	__asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")

#define smp_rmb()	__asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
@@ -129,4 +134,8 @@ 
#define set_mb(var, value) \

	do { var = value; smp_mb(); } while (0)



#define smp_llsc_mb()	__asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")

#define smp_llsc_rmb()	__asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")

#define smp_llsc_wmb()	__asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")



#endif /* __ASM_BARRIER_H */