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Commit 0268099c authored by Gabriel FERNANDEZ's avatar Gabriel FERNANDEZ Committed by Mike Turquette
Browse files

clk: st: Update ST clock binding documentation 



Naming convention was changed in dts file but the
clock binding documentation hasn't been updated.

Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 381c1ccd

Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt

+14 −14
Original line number Diff line number Diff line
@@ -24,26 +24,26 @@ Required properties: 


Example:



	clockgenA@fd345000 {

	clockgen-a@fd345000 {

		reg = <0xfd345000 0xb50>;



		CLK_M_A1_DIV1: CLK_M_A1_DIV1 {

		clk_m_a1_div1: clk-m-a1-div1 {

			#clock-cells = <1>;

			compatible = "st,clkgena-divmux-c32-odf1",

				     "st,clkgena-divmux";



			clocks = <&CLK_M_A1_OSC_PREDIV>,

				 <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */

				 <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */



			clock-output-names = "CLK_M_RX_ICN_TS",

					     "CLK_M_RX_ICN_VDP_0",

					     "", /* Unused */

					     "CLK_M_PRV_T1_BUS",

					     "CLK_M_ICN_REG_12",

					     "CLK_M_ICN_REG_10",

					     "", /* Unused */

					     "CLK_M_ICN_ST231";

			clocks = <&clk_m_a1_osc_prediv>,

				 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */

				 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */



			clock-output-names = "clk-m-rx-icn-ts",

					     "clk-m-rx-icn-vdp-0",

					     "", /* unused */

					     "clk-m-prv-t1-bus",

					     "clk-m-icn-reg-12",

					     "clk-m-icn-reg-10",

					     "", /* unused */

					     "clk-m-icn-st231";

		};

	};

Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt

+3 −3
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ Required properties: 
	"st,stih416-clkgenf-vcc-sd",	"st,clkgen-mux"

	"st,stih415-clkgen-a9-mux",	"st,clkgen-mux"

	"st,stih416-clkgen-a9-mux",	"st,clkgen-mux"



	"st,stih407-clkgen-a9-mux",	"st,clkgen-mux"



- #clock-cells : from common clock binding; shall be set to 0.
@@ -27,10 +27,10 @@ Required properties: 


Example:



	CLK_M_HVA: CLK_M_HVA {

	clk_m_hva: clk-m-hva@fd690868 {

		#clock-cells = <0>;

		compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";

		reg = <0xfd690868 4>;



		clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;

		clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;

	};

Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt

+10 −7
Original line number Diff line number Diff line
@@ -19,11 +19,14 @@ Required properties: 
	"st,stih415-plls-c32-ddr",	"st,clkgen-plls-c32"

	"st,stih416-plls-c32-a9",	"st,clkgen-plls-c32"

	"st,stih416-plls-c32-ddr",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-a0",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-a9",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-c0_0",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-c0_1",	"st,clkgen-plls-c32"



	"st,stih415-gpu-pll-c32",	"st,clkgengpu-pll-c32"

	"st,stih416-gpu-pll-c32",	"st,clkgengpu-pll-c32"





- #clock-cells : From common clock binding; shall be set to 1.



- clocks : From common clock binding
@@ -32,17 +35,17 @@ Required properties: 


Example:



	clockgenA@fee62000 {

	clockgen-a@fee62000 {

		reg = <0xfee62000 0xb48>;



		CLK_S_A0_PLL: CLK_S_A0_PLL {

		clk_s_a0_pll: clk-s-a0-pll {

			#clock-cells = <1>;

			compatible = "st,clkgena-plls-c65";



			clocks = <&CLK_SYSIN>;

			clocks = <&clk_sysin>;



			clock-output-names = "CLK_S_A0_PLL0_HS",

					     "CLK_S_A0_PLL0_LS",

					     "CLK_S_A0_PLL1";

			clock-output-names = "clk-s-a0-pll0-hs",

					     "clk-s-a0-pll0-ls",

					     "clk-s-a0-pll1";

		};

	};

Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt

+4 −4
Original line number Diff line number Diff line
@@ -20,17 +20,17 @@ Required properties: 


Example:



	clockgenA@fd345000 {

	clockgen-a@fd345000 {

		reg = <0xfd345000 0xb50>;



		CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {

		clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {

			#clock-cells = <0>;

			compatible = "st,clkgena-prediv-c32",

				     "st,clkgena-prediv";



			clocks = <&CLK_SYSIN>;

			clocks = <&clk_sysin>;



			clock-output-names = "CLK_M_A2_OSC_PREDIV";

			clock-output-names = "clk-m-a2-osc-prediv";

		};

	};

Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt

+21 −13
Original line number Diff line number Diff line
@@ -32,22 +32,30 @@ Required properties: 


Example:



	CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {

	clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {

		#clock-cells = <1>;

		compatible = "st,stih416-clkgenc", "st,clkgen-vcc";

		reg = <0xfe8308ac 12>;



		clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,

			<&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;



		clock-output-names  =

			"CLK_S_PIX_HDMI",  "CLK_S_PIX_DVO",

			"CLK_S_OUT_DVO",   "CLK_S_PIX_HD",

			"CLK_S_HDDAC",     "CLK_S_DENC",

			"CLK_S_SDDAC",     "CLK_S_PIX_MAIN",

			"CLK_S_PIX_AUX",   "CLK_S_STFE_FRC_0",

			"CLK_S_REF_MCRU",  "CLK_S_SLAVE_MCRU",

			"CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",

			"CLK_S_THSENS";

		clocks = <&clk_s_vcc_hd>,

			 <&clockgen_c 1>,

			 <&clk_s_tmds_fromphy>,

			 <&clockgen_c 2>;



		clock-output-names  = "clk-s-pix-hdmi",

				      "clk-s-pix-dvo",

				      "clk-s-out-dvo",

				      "clk-s-pix-hd",

				      "clk-s-hddac",

				      "clk-s-denc",

				      "clk-s-sddac",

				      "clk-s-pix-main",

				      "clk-s-pix-aux",

				      "clk-s-stfe-frc-0",

				      "clk-s-ref-mcru",

				      "clk-s-slave-mcru",

				      "clk-s-tmds-hdmi",

				      "clk-s-hdmi-reject-pll",

				      "clk-s-thsens";

	};