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Commit 0166f312 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: gcc-sdm845: Add the BRANCH_VOTED flag to the GCC GPU clocks 



The gcc_ddrss_gpu_axi_clk and gcc_gpu_memnoc_gfx_clk clocks are
controllable from the GPU SMMU clock voting registers. This might
lead them to remain enabled even after removing the SW vote on the
CBCRs.
Changing the halt_check to BRANCH_VOTED takes care of polling the
status bits of these CBCRs only while enabling these clocks.

Change-Id: I1568c471a5fbeffb3193f0f49519f7dfde71c8fa
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent a471cbd8

drivers/clk/qcom/gcc-sdm855.c

+3 −3
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -1975,7 +1975,7 @@ static struct clk_branch gcc_cpuss_rbcpr_clk = { 


static struct clk_branch gcc_ddrss_gpu_axi_clk = {

	.halt_reg = 0x71154,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_VOTED,

	.clkr = {

		.enable_reg = 0x71154,

		.enable_mask = BIT(0),
@@ -2225,7 +2225,7 @@ static struct clk_branch gcc_gpu_iref_clk = { 


static struct clk_branch gcc_gpu_memnoc_gfx_clk = {

	.halt_reg = 0x7100c,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_VOTED,

	.clkr = {

		.enable_reg = 0x7100c,

		.enable_mask = BIT(0),