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Commit 00d70b15 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: skip redundant operations whilst enabling pipes and planes 

If the pipe or plane is already enabled, then we do not need to enable
it again and can skip the delay. Similarly if it is already disabled
when we want to disable it, we can also skip it.

This fixes a regression from b24e7179, which caused the LVDS
output on one PineView machine to become corrupt after changing
orientation several times.

References: https://bugs.freedesktop.org/show_bug.cgi?id=34601


Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarKeith Packard <keithp@keithp.com>
Tested-by: default avatar <mengmeng.meng@intel.com>
parent 762237bb

drivers/gpu/drm/i915/intel_display.c

+16 −8
Original line number Diff line number Diff line
@@ -1516,8 +1516,10 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, 


	reg = PIPECONF(pipe);

	val = I915_READ(reg);

	val |= PIPECONF_ENABLE;

	I915_WRITE(reg, val);

	if (val & PIPECONF_ENABLE)

		return;



	I915_WRITE(reg, val | PIPECONF_ENABLE);

	intel_wait_for_vblank(dev_priv->dev, pipe);

}
@@ -1551,8 +1553,10 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv, 


	reg = PIPECONF(pipe);

	val = I915_READ(reg);

	val &= ~PIPECONF_ENABLE;

	I915_WRITE(reg, val);

	if ((val & PIPECONF_ENABLE) == 0)

		return;



	I915_WRITE(reg, val & ~PIPECONF_ENABLE);

	intel_wait_for_pipe_off(dev_priv->dev, pipe);

}
@@ -1575,8 +1579,10 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv, 


	reg = DSPCNTR(plane);

	val = I915_READ(reg);

	val |= DISPLAY_PLANE_ENABLE;

	I915_WRITE(reg, val);

	if (val & DISPLAY_PLANE_ENABLE)

		return;



	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);

	intel_wait_for_vblank(dev_priv->dev, pipe);

}
@@ -1607,8 +1613,10 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv, 


	reg = DSPCNTR(plane);

	val = I915_READ(reg);

	val &= ~DISPLAY_PLANE_ENABLE;

	I915_WRITE(reg, val);

	if ((val & DISPLAY_PLANE_ENABLE) == 0)

		return;



	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);

	intel_flush_display_plane(dev_priv, plane);

	intel_wait_for_vblank(dev_priv->dev, pipe);

}