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Commit ffb75a84 authored by George Shen's avatar George Shen
Browse files

msm: cvp: Support LPDDR4/5 configuration for CVP 



Highest bank bit of UBWC config is different for
LPDDR4 and LPDDR5. Get CVP the configuration to
work properly.

Change-Id: I9640e9a21a775b110c97330dd3860213b6c1da09
Signed-off-by: default avatarGeorge Shen <sqiao@codeaurora.org>
parent fd5a2f0d

drivers/media/platform/msm/cvp/cvp_hfi.c

+33 −1
Original line number Diff line number Diff line
@@ -105,6 +105,8 @@ static void interrupt_init_vpu5(struct venus_hfi_device *device); 
static void setup_dsp_uc_memmap_vpu5(struct venus_hfi_device *device);

static void clock_config_on_enable_vpu5(struct venus_hfi_device *device);



static int __set_ubwc_config(struct venus_hfi_device *device);



struct venus_hfi_vpu_ops cvp_vpu4_ops = {

	.interrupt_init = interrupt_init_vpu4,

	.setup_dsp_uc_memmap = NULL,
@@ -2064,9 +2066,10 @@ static int venus_hfi_core_init(void *device) 


	__enable_subcaches(device);

	__set_subcaches(device);



	__dsp_send_hfi_queue(device);



	__set_ubwc_config(device);



	if (dev->res->pm_qos_latency_us) {

#ifdef CONFIG_SMP

		dev->qos.type = PM_QOS_REQ_AFFINE_IRQ;
@@ -4113,6 +4116,35 @@ static void clock_config_on_enable_vpu5(struct venus_hfi_device *device) 
		__write_register(device, CVP_WRAPPER_CPU_CLOCK_CONFIG, 0);

}



static int __set_ubwc_config(struct venus_hfi_device *device)

{

	u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];

	int rc = 0;



	struct hfi_cmd_sys_set_property_packet *pkt =

		(struct hfi_cmd_sys_set_property_packet *) &packet;



	if (!device->res->ubwc_config)

		return 0;



	rc = call_hfi_pkt_op(device, sys_ubwc_config, pkt,

		device->res->ubwc_config);

	if (rc) {

		dprintk(CVP_WARN,

			"ubwc config setting to FW failed\n");

		rc = -ENOTEMPTY;

		goto fail_to_set_ubwc_config;

	}



	if (__iface_cmdq_write(device, pkt)) {

		rc = -ENOTEMPTY;

		goto fail_to_set_ubwc_config;

	}



fail_to_set_ubwc_config:

	return rc;

}



static int __venus_power_on(struct venus_hfi_device *device)

{

	int rc = 0;

drivers/media/platform/msm/cvp/cvp_hfi_helper.h

+21 −0
Original line number Diff line number Diff line
@@ -196,6 +196,8 @@ struct hfi_buffer_info { 
	(HFI_PROPERTY_SYS_COMMON_START + 0x006)

#define  HFI_PROPERTY_SYS_CONFIG_COVERAGE    \

	(HFI_PROPERTY_SYS_COMMON_START + 0x007)

#define  HFI_PROPERTY_SYS_UBWC_CONFIG    \

	(HFI_PROPERTY_SYS_COMMON_START + 0x008)



#define HFI_PROPERTY_PARAM_COMMON_START	\

	(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x1000)
@@ -966,6 +968,25 @@ struct hfi_cmd_sys_set_buffers_packet { 
	u32 rg_buffer_addr[1];

};



struct hfi_cmd_sys_set_ubwc_config_packet_type {

	u32 size;

	u32 packet_type;

	struct {

		u32 max_channel_override : 1;

		u32 mal_length_override : 1;

		u32 hb_override : 1;

		u32 bank_swzl_level_override : 1;

		u32 bank_spreading_override : 1;

		u32 reserved : 27;

	} override_bit_info;

	u32 max_channels;

	u32 mal_length;

	u32 highest_bank_bit;

	u32 bank_swzl_level;

	u32 bank_spreading;

	u32 reserved[2];

};



struct hfi_cmd_session_set_property_packet {

	u32 size;

	u32 packet_type;

drivers/media/platform/msm/cvp/hfi_packetization.c

+44 −0
Original line number Diff line number Diff line
@@ -426,6 +426,49 @@ inline int cvp_create_pkt_cmd_sys_session_init( 
	return rc;

}



static int create_pkt_cmd_sys_ubwc_config(

		struct hfi_cmd_sys_set_property_packet *pkt,

		struct msm_cvp_ubwc_config_data *ubwc_config)

{

	int rc = 0;

	struct hfi_cmd_sys_set_ubwc_config_packet_type *hfi;



	if (!pkt)

		return -EINVAL;



	pkt->size = sizeof(struct hfi_cmd_sys_set_property_packet) +

		sizeof(struct hfi_cmd_sys_set_ubwc_config_packet_type)

		+ sizeof(u32);



	pkt->packet_type = HFI_CMD_SYS_SET_PROPERTY;

	pkt->num_properties = 1;

	pkt->rg_property_data[0] = HFI_PROPERTY_SYS_UBWC_CONFIG;

	hfi = (struct hfi_cmd_sys_set_ubwc_config_packet_type *)

		&pkt->rg_property_data[1];



	hfi->max_channels = ubwc_config->max_channels;

	hfi->override_bit_info.max_channel_override =

		ubwc_config->override_bit_info.max_channel_override;



	hfi->mal_length = ubwc_config->mal_length;

	hfi->override_bit_info.mal_length_override =

		ubwc_config->override_bit_info.mal_length_override;



	hfi->highest_bank_bit = ubwc_config->highest_bank_bit;

	hfi->override_bit_info.hb_override =

		ubwc_config->override_bit_info.hb_override;



	hfi->bank_swzl_level = ubwc_config->bank_swzl_level;

	hfi->override_bit_info.bank_swzl_level_override =

		ubwc_config->override_bit_info.bank_swzl_level_override;



	hfi->bank_spreading = ubwc_config->bank_spreading;

	hfi->override_bit_info.bank_spreading_override =

		ubwc_config->override_bit_info.bank_spreading_override;



	return rc;

}



int cvp_create_pkt_cmd_session_cmd(struct cvp_hal_session_cmd_pkt *pkt,

			int pkt_type, struct hal_session *session)

{
@@ -2163,6 +2206,7 @@ static struct hfi_packetization_ops hfi_default = { 
	.sys_release_resource = cvp_create_pkt_cmd_sys_release_resource,

	.sys_ping = cvp_create_pkt_cmd_sys_ping,

	.sys_image_version = cvp_create_pkt_cmd_sys_image_version,

	.sys_ubwc_config = create_pkt_cmd_sys_ubwc_config,

	.ssr_cmd = cvp_create_pkt_ssr_cmd,

	.session_init = cvp_create_pkt_cmd_sys_session_init,

	.session_cmd = cvp_create_pkt_cmd_session_cmd,

drivers/media/platform/msm/cvp/hfi_packetization.h

+2 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ struct hfi_packetization_ops { 
		struct cvp_resource_hdr *resource_hdr);

	int (*sys_ping)(struct hfi_cmd_sys_ping_packet *pkt);

	int (*sys_image_version)(struct hfi_cmd_sys_get_property_packet *pkt);

	int (*sys_ubwc_config)(struct hfi_cmd_sys_set_property_packet *pkt,

		struct msm_cvp_ubwc_config_data *ubwc_config);

	int (*ssr_cmd)(enum hal_ssr_trigger_type type,

		struct hfi_cmd_sys_test_ssr_packet *pkt);

	int (*session_init)(

drivers/media/platform/msm/cvp/msm_cvp_internal.h

+18 −0
Original line number Diff line number Diff line
@@ -221,6 +221,23 @@ enum vpu_version { 
	VPU_VERSION_5,

};



struct msm_cvp_ubwc_config_data {

	struct {

		u32 max_channel_override : 1;

		u32 mal_length_override : 1;

		u32 hb_override : 1;

		u32 bank_swzl_level_override : 1;

		u32 bank_spreading_override : 1;

		u32 reserved : 27;

	} override_bit_info;



	u32 max_channels;

	u32 mal_length;

	u32 highest_bank_bit;

	u32 bank_swzl_level;

	u32 bank_spreading;

};



#define IS_VPU_4(ver) \

	(ver == VPU_VERSION_4)
@@ -239,6 +256,7 @@ struct msm_cvp_platform_data { 
	phys_addr_t gcc_register_base;

	uint32_t gcc_register_size;

	uint32_t vpu_ver;

	struct msm_cvp_ubwc_config_data *ubwc_config;

};



struct msm_cvp_format {