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Commit ff1c516e authored by Baruch Siach's avatar Baruch Siach Committed by Gregory CLEMENT
Browse files

arm64: dts: marvell: add CP110 uart peripherals 



The CP110 component has 4 uart peripherals. All of them use the same clock
gate for slow peripherals that is shared with the i2c and spi peripherals.

Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
parent afe8e5a9

arch/arm64/boot/dts/marvell/armada-cp110.dtsi

+40 −0
Original line number Diff line number Diff line
@@ -298,6 +298,46 @@ 
			status = "disabled";

		};



		CP110_LABEL(uart0): serial@702000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x702000 0x100>;

			reg-shift = <2>;

			interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;

			reg-io-width = <1>;

			clocks = <&CP110_LABEL(clk) 1 21>;

			status = "disabled";

		};



		CP110_LABEL(uart1): serial@702100 {

			compatible = "snps,dw-apb-uart";

			reg = <0x702100 0x100>;

			reg-shift = <2>;

			interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;

			reg-io-width = <1>;

			clocks = <&CP110_LABEL(clk) 1 21>;

			status = "disabled";

		};



		CP110_LABEL(uart2): serial@702200 {

			compatible = "snps,dw-apb-uart";

			reg = <0x702200 0x100>;

			reg-shift = <2>;

			interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;

			reg-io-width = <1>;

			clocks = <&CP110_LABEL(clk) 1 21>;

			status = "disabled";

		};



		CP110_LABEL(uart3): serial@702300 {

			compatible = "snps,dw-apb-uart";

			reg = <0x702300 0x100>;

			reg-shift = <2>;

			interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;

			reg-io-width = <1>;

			clocks = <&CP110_LABEL(clk) 1 21>;

			status = "disabled";

		};



		CP110_LABEL(nand): nand@720000 {

			/*

			* Due to the limitation of the pins available