Merge "drm/msm/sde: add sui blendstage and QoS FL caps for kona" (ff02fded) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+13 −7

Original line number	Diff line number	Diff line
		@@ -3778,6 +3778,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
		sde_cfg->sui_ns_allowed = true;
		sde_cfg->sui_misr_supported = true;
		sde_cfg->sui_block_xin_mask = 0x3F71;
		sde_cfg->has_sui_blendstage = true;
		sde_cfg->has_qos_fl_nocalc = true;
		sde_cfg->has_3d_merge_reset = true;
		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
		@@ -3806,6 +3808,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
		sde_cfg->sui_misr_supported = true;
		sde_cfg->has_decimation = true;
		sde_cfg->sui_block_xin_mask = 0x2EE1;
		sde_cfg->has_sui_blendstage = true;
		sde_cfg->has_qos_fl_nocalc = true;
		sde_cfg->has_3d_merge_reset = true;
		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
		@@ -3823,6 +3827,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
		sde_cfg->sui_ns_allowed = true;
		sde_cfg->sui_misr_supported = true;
		sde_cfg->sui_block_xin_mask = 0xE71;
		sde_cfg->has_sui_blendstage = true;
		sde_cfg->has_qos_fl_nocalc = true;
		sde_cfg->has_3d_merge_reset = true;
		} else if (IS_KONA_TARGET(hw_rev)) {
		sde_cfg->has_cwb_support = true;
		@@ -3836,6 +3842,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
		sde_cfg->sui_ns_allowed = true;
		sde_cfg->sui_misr_supported = true;
		sde_cfg->sui_block_xin_mask = 0x3F71;
		sde_cfg->has_sui_blendstage = true;
		sde_cfg->has_qos_fl_nocalc = true;
		sde_cfg->has_3d_merge_reset = true;
		clear_bit(MDSS_INTR_AD4_0_INTR, sde_cfg->mdss_irqs);
		clear_bit(MDSS_INTR_AD4_1_INTR, sde_cfg->mdss_irqs);
		@@ -3875,16 +3883,10 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg,
		if (!sde_cfg)
		return -EINVAL;

		if (IS_SM8150_TARGET(hw_rev) \|\| IS_SM6150_TARGET(hw_rev) \|\|
		IS_SDMMAGPIE_TARGET(hw_rev)) {
		if (sde_cfg->has_sui_blendstage)
		sde_cfg->sui_supported_blendstage =
		sde_cfg->max_mixer_blendstages - SDE_STAGE_0;

		for (i = 0; i < sde_cfg->sspp_count; i++)
		set_bit(SDE_PERF_SSPP_QOS_FL_NOCALC,
		&sde_cfg->sspp[i].perf_features);
		}

		for (i = 0; i < sde_cfg->sspp_count; i++) {
		if (sde_cfg->sspp[i].sblk) {
		max_horz_deci = max(max_horz_deci,
		@@ -3893,6 +3895,10 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg,
		sde_cfg->sspp[i].sblk->maxvdeciexp);
		}

		if (sde_cfg->has_qos_fl_nocalc)
		set_bit(SDE_PERF_SSPP_QOS_FL_NOCALC,
		&sde_cfg->sspp[i].perf_features);

		/*
		* set sec-ui blocked SSPP feature flag based on blocked
		* xin-mask if sec-ui-misr feature is enabled;

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -1197,6 +1197,7 @@ struct sde_perf_cfg {
		* @has_qsync Supports qsync feature
		* @has_3d_merge_reset Supports 3D merge reset
		* @has_decimation Supports decimation
		* @has_qos_fl_nocalc flag to indicate QoS fill level needs no calculation
		* @sc_cfg: system cache configuration
		* @uidle_cfg Settings for uidle feature
		* @sui_misr_supported indicate if secure-ui-misr is supported
		@@ -1208,6 +1209,7 @@ struct sde_perf_cfg {
		* @sui_ns_allowed flag to indicate non-secure context banks are allowed
		* during secure-ui session
		* @sui_supported_blendstage secure-ui supported blendstage
		* @has_sui_blendstage flag to indicate secure-ui has a blendstage restriction
		* @has_cursor indicates if hardware cursor is supported
		* @has_vig_p010 indicates if vig pipe supports p010 format
		* @inline_rot_formats formats supported by the inline rotator feature
		@@ -1253,6 +1255,7 @@ struct sde_mdss_cfg {
		bool has_qsync;
		bool has_3d_merge_reset;
		bool has_decimation;
		bool has_qos_fl_nocalc;

		struct sde_sc_cfg sc_cfg;

		@@ -1263,6 +1266,7 @@ struct sde_mdss_cfg {
		u32 sec_sid_mask[MAX_BLOCKS];
		u32 sui_ns_allowed;
		u32 sui_supported_blendstage;
		bool has_sui_blendstage;

		bool has_hdr;
		bool has_hdr_plus;