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Commit fe53d144 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull ARM SoC driver updates from Arnd Bergmann:
 "A number of new drivers get added this time, along with many
  low-priority bugfixes. The most interesting changes by subsystem are:

  bus drivers:
   - Updates to the Broadcom bus interface driver to support newer SoC
     types
   - The TI OMAP sysc driver now supports updated DT bindings

  memory controllers:
   - A new driver for Tegra186 gets added
   - A new driver for the ti-emif sram, to allow relocating
     suspend/resume handlers there

  SoC specific:
   - A new driver for Qualcomm QMI, the interface to the modem on MSM
     SoCs
   - A new driver for power domains on the actions S700 SoC
   - A driver for the Xilinx Zynq VCU logicoreIP

  reset controllers:
   - A new driver for Amlogic Meson-AGX
   - various bug fixes

  tee subsystem:
   - A new user interface got added to enable asynchronous communication
     with the TEE supplicant.
   - A new method of using user space memory for communication with the
     TEE is added"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (84 commits)
  of: platform: fix OF node refcount leak
  soc: fsl: guts: Add a NULL check for devm_kasprintf()
  bus: ti-sysc: Fix smartreflex sysc mask
  psci: add CPU_IDLE dependency
  soc: xilinx: Fix Kconfig alignment
  soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv
  soc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcu
  soc: bcm: brcmstb: Be multi-platform compatible
  soc: brcmstb: biuctrl: exit without warning on non brcmstb platforms
  Revert "soc: brcmstb: Only register SoC device on STB platforms"
  bus: omap: add MODULE_LICENSE tags
  soc: brcmstb: Only register SoC device on STB platforms
  tee: shm: Potential NULL dereference calling tee_shm_register()
  soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
  dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver
  soc: xilinx: Create folder structure for soc specific drivers
  of: platform: populate /firmware/ node from of_platform_default_populate_init()
  soc: samsung: Add SPDX license identifiers
  soc: qcom: smp2p: Use common error handling code in qcom_smp2p_probe()
  tee: shm: don't put_page on null shm->pages
  ...
parents adbc128f 796543a6
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+12 −10
Original line number Diff line number Diff line
@@ -17,21 +17,23 @@ Further, syscon nodes that map platform-specific registers used for general
system control is required:

    - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
    - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
    - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
		  "brcm,brcmstb-cpu-biu-ctrl",
		  "syscon"
    - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"

hif-cpubiuctrl node
cpu-biu-ctrl node
-------------------
SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit
(BIU) block which controls and interfaces the CPU complex to the different
Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block
offers a feature called Write Pairing which consists in collapsing two adjacent
cache lines into a single (bursted) write transaction towards the memory
controller (MEMC) to maximize write bandwidth.
SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
complex to the different Memory Controller Ports (MCP), one per memory
controller (MEMC). This BIU block offers a feature called Write Pairing which
consists in collapsing two adjacent cache lines into a single (bursted) write
transaction towards the memory controller (MEMC) to maximize write bandwidth.

Required properties:

    - compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"
    - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"

Optional properties:

@@ -52,7 +54,7 @@ example:
        };

        hif_cpubiuctrl: syscon@3e2400 {
            compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
            compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
            reg = <0x3e2400 0x5b4>;
            brcm,write-pairing;
        };
+1 −0
Original line number Diff line number Diff line
@@ -169,6 +169,7 @@ described below.
			    "arm,cortex-r5"
			    "arm,cortex-r7"
			    "brcm,brahma-b15"
			    "brcm,brahma-b53"
			    "brcm,vulcan"
			    "cavium,thunder"
			    "cavium,thunder2"
+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ Required standard properties:

- compatible	shall be one of the following generic types:

		"ti,sysc"
		"ti,sysc-omap2"
		"ti,sysc-omap4"
		"ti,sysc-omap4-simple"
+16 −1
Original line number Diff line number Diff line
@@ -23,6 +23,13 @@ Required properties:
  the value shall be "emif<n>" where <n> is the number of the EMIF
  instance with base 1.

Required only for "ti,emif-am3352" and "ti,emif-am4372":
- sram			: Phandles for generic sram driver nodes,
  first should be type 'protect-exec' for the driver to use to copy
  and run PM functions, second should be regular pool to be used for
  data region for code. See Documentation/devicetree/bindings/sram/sram.txt
  for more details.

Optional properties:
- cs1-used		: Have this property if CS1 of this EMIF
  instance has a memory part attached to it. If there is a memory
@@ -44,7 +51,7 @@ Optional properties:
- hw-caps-temp-alert	: Have this property if the controller
  has capability for generating SDRAM temperature alerts

Example:
-Examples:

emif1: emif@4c000000 {
	compatible	= "ti,emif-4d";
@@ -56,3 +63,11 @@ emif1: emif@4c000000 {
	hw-caps-ll-interface;
	hw-caps-temp-alert;
};

/* From am33xx.dtsi */
emif: emif@4c000000 {
        compatible = "ti,emif-am3352";
        reg =   <0x4C000000 0x1000>;
        sram = <&pm_sram_code
                &pm_sram_data>;
};
+3 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required properties:
  - fsl,imx6q-gpc
  - fsl,imx6qp-gpc
  - fsl,imx6sl-gpc
  - fsl,imx6sx-gpc
- reg: should be register base and length as documented in the
  datasheet
- interrupts: Should contain one interrupt specifier for the GPC interrupt
@@ -29,6 +30,8 @@ Required properties:
  PU_DOMAIN      1
  The following additional DOMAIN_INDEX value is valid for i.MX6SL:
  DISPLAY_DOMAIN 2
  The following additional DOMAIN_INDEX value is valid for i.MX6SX:
  PCI_DOMAIN     3

- #power-domain-cells: Should be 0

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