Loading drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +9 −9 Original line number Diff line number Diff line Loading @@ -2167,7 +2167,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping true, IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, QMB_MASTER_SELECT_DDR, { 2, 7, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 8 } }, { 2, 7, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 } }, [IPA_4_5][IPA_CLIENT_APPS_CMD_PROD] = { true, IPA_v4_5_GROUP_UL_DL, false, Loading @@ -2179,13 +2179,13 @@ static const struct ipa_ep_configuration ipa3_ep_mapping true, IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, QMB_MASTER_SELECT_DDR, { 10, 13, 8, 19, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, { 3, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } }, [IPA_4_5][IPA_CLIENT_ETHERNET_PROD] = { true, IPA_v4_5_GROUP_UL_DL, true, IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, QMB_MASTER_SELECT_DDR, { 12, 0, 8, 16, IPA_EE_UC, GSI_SMART_PRE_FETCH, 4 } }, { 12, 0, 8, 16, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3 } }, [IPA_4_5][IPA_CLIENT_Q6_WAN_PROD] = { true, IPA_v4_5_GROUP_UL_DL, true, Loading Loading @@ -2241,7 +2241,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 24, 3, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, { 24, 3, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } }, [IPA_4_5][IPA_CLIENT_USB_CONS] = { true, IPA_v4_5_GROUP_UL_DL, false, Loading Loading @@ -2271,7 +2271,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 13, 4, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, { 13, 4, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } }, [IPA_4_5][IPA_CLIENT_APPS_WAN_CONS] = { true, IPA_v4_5_GROUP_UL_DL, false, Loading @@ -2283,7 +2283,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 23, 8, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, { 30, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, [IPA_4_5][IPA_CLIENT_ETHERNET_CONS] = { true, IPA_v4_5_GROUP_UL_DL, false, Loading Loading @@ -2390,13 +2390,13 @@ static const struct ipa_ep_configuration ipa3_ep_mapping false, IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, QMB_MASTER_SELECT_DDR, { 4, 8, 8, 16, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 4 } }, { 4, 8, 8, 16, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 3 } }, [IPA_4_5_MHI][IPA_CLIENT_MHI_PROD] = { true, IPA_v4_5_MHI_GROUP_PCIE, true, IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, QMB_MASTER_SELECT_PCIE, { 1, 0, 16, 20, IPA_EE_AP, GSI_SMART_PRE_FETCH, 8 } }, { 1, 0, 16, 20, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 } }, [IPA_4_5_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD] = { true, IPA_v4_5_MHI_GROUP_DMA, false, Loading Loading @@ -2463,7 +2463,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping true, IPA_v4_5_MHI_GROUP_DMA, false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, QMB_MASTER_SELECT_PCIE, { 29, 9, 9, 9, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 4 } }, [IPA_4_5_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS] = { true, IPA_v4_5_MHI_GROUP_DMA, Loading Loading
drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +9 −9 Original line number Diff line number Diff line Loading @@ -2167,7 +2167,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping true, IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, QMB_MASTER_SELECT_DDR, { 2, 7, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 8 } }, { 2, 7, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 } }, [IPA_4_5][IPA_CLIENT_APPS_CMD_PROD] = { true, IPA_v4_5_GROUP_UL_DL, false, Loading @@ -2179,13 +2179,13 @@ static const struct ipa_ep_configuration ipa3_ep_mapping true, IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, QMB_MASTER_SELECT_DDR, { 10, 13, 8, 19, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, { 3, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } }, [IPA_4_5][IPA_CLIENT_ETHERNET_PROD] = { true, IPA_v4_5_GROUP_UL_DL, true, IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, QMB_MASTER_SELECT_DDR, { 12, 0, 8, 16, IPA_EE_UC, GSI_SMART_PRE_FETCH, 4 } }, { 12, 0, 8, 16, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3 } }, [IPA_4_5][IPA_CLIENT_Q6_WAN_PROD] = { true, IPA_v4_5_GROUP_UL_DL, true, Loading Loading @@ -2241,7 +2241,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 24, 3, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, { 24, 3, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } }, [IPA_4_5][IPA_CLIENT_USB_CONS] = { true, IPA_v4_5_GROUP_UL_DL, false, Loading Loading @@ -2271,7 +2271,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 13, 4, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, { 13, 4, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } }, [IPA_4_5][IPA_CLIENT_APPS_WAN_CONS] = { true, IPA_v4_5_GROUP_UL_DL, false, Loading @@ -2283,7 +2283,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 23, 8, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, { 30, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, [IPA_4_5][IPA_CLIENT_ETHERNET_CONS] = { true, IPA_v4_5_GROUP_UL_DL, false, Loading Loading @@ -2390,13 +2390,13 @@ static const struct ipa_ep_configuration ipa3_ep_mapping false, IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, QMB_MASTER_SELECT_DDR, { 4, 8, 8, 16, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 4 } }, { 4, 8, 8, 16, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 3 } }, [IPA_4_5_MHI][IPA_CLIENT_MHI_PROD] = { true, IPA_v4_5_MHI_GROUP_PCIE, true, IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, QMB_MASTER_SELECT_PCIE, { 1, 0, 16, 20, IPA_EE_AP, GSI_SMART_PRE_FETCH, 8 } }, { 1, 0, 16, 20, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 } }, [IPA_4_5_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD] = { true, IPA_v4_5_MHI_GROUP_DMA, false, Loading Loading @@ -2463,7 +2463,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping true, IPA_v4_5_MHI_GROUP_DMA, false, IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, QMB_MASTER_SELECT_PCIE, { 29, 9, 9, 9, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 4 } }, [IPA_4_5_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS] = { true, IPA_v4_5_MHI_GROUP_DMA, Loading