Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fe2edd9c authored by Alexandre Belloni's avatar Alexandre Belloni
Browse files

Documentation: dt: atmel-at91: add clocks to system timer, rstc and shdwc 



The system timer (at91rm9200), the reset controller and the shutdown
controller need an input clock. This is the slow clock and they will not
function without it.

Also fix the shutdown controller example.

Acked-By: default avatarSebastian Reichel <sre@kernel.org>
Acked-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
parent 22b5a0f7

Documentation/devicetree/bindings/arm/atmel-at91.txt

+8 −3
Original line number Original line Diff line number Diff line
@@ -50,6 +50,7 @@ System Timer (ST) required properties: 
- reg: Should contain registers location and length

- reg: Should contain registers location and length

- interrupts: Should contain interrupt for the ST which is the IRQ line

- interrupts: Should contain interrupt for the ST which is the IRQ line

  shared across all System Controller members.

  shared across all System Controller members.

- clocks: phandle to input clock.

Its subnodes can be:

Its subnodes can be:

- watchdog: compatible should be "atmel,at91rm9200-wdt"

- watchdog: compatible should be "atmel,at91rm9200-wdt"
@@ -89,12 +90,14 @@ RSTC Reset Controller required properties: 
- compatible: Should be "atmel,<chip>-rstc".

- compatible: Should be "atmel,<chip>-rstc".

  <chip> can be "at91sam9260" or "at91sam9g45"

  <chip> can be "at91sam9260" or "at91sam9g45"

- reg: Should contain registers location and length

- reg: Should contain registers location and length

- clocks: phandle to input clock.





Example:

Example:





	rstc@fffffd00 {

	rstc@fffffd00 {

		compatible = "atmel,at91sam9260-rstc";

		compatible = "atmel,at91sam9260-rstc";

		reg = <0xfffffd00 0x10>;

		reg = <0xfffffd00 0x10>;

		clocks = <&clk32k>;

	};

	};





RAMC SDRAM/DDR Controller required properties:

RAMC SDRAM/DDR Controller required properties:
@@ -117,6 +120,7 @@ required properties: 
- compatible: Should be "atmel,<chip>-shdwc".

- compatible: Should be "atmel,<chip>-shdwc".

  <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".

  <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".

- reg: Should contain registers location and length

- reg: Should contain registers location and length

- clocks: phandle to input clock.





optional properties:

optional properties:

- atmel,wakeup-mode: String, operation mode of the wakeup mode.

- atmel,wakeup-mode: String, operation mode of the wakeup mode.
@@ -135,9 +139,10 @@ optional at91sam9x5 properties: 




Example:

Example:





	rstc@fffffd00 {

	shdwc@fffffd10 {

		compatible = "atmel,at91sam9260-rstc";

		compatible = "atmel,at91sam9260-shdwc";

		reg = <0xfffffd00 0x10>;

		reg = <0xfffffd10 0x10>;

		clocks = <&clk32k>;

	};

	};





Special Function Registers (SFR)

Special Function Registers (SFR)