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Commit fd451b90 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

arm64: KVM: vgic-v3: Restore ICH_APR0Rn_EL2 before ICH_APR1Rn_EL2 



The GICv3 architecture spec says:

Writing to the active priority registers in any order other than
the following order will result in UNPREDICTABLE behavior:
- ICH_AP0R<n>_EL2.
- ICH_AP1R<n>_EL2.

So let's not pointlessly go against the rule...

Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 1d6a8212

arch/arm64/kvm/hyp/vgic-v3-sr.c

+10 −10
Original line number Original line Diff line number Diff line
@@ -149,22 +149,22 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu) 




	switch (nr_pri_bits) {

	switch (nr_pri_bits) {

	case 7:

	case 7:

		 write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2);

		 write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2);

		 write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2);

		 write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2);

	case 6:

	case 6:

		 write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2);

		 write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2);

	default:

	default:

		 write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2);

		 write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2);

	}

	}





	switch (nr_pri_bits) {

	switch (nr_pri_bits) {

	case 7:

	case 7:

		 write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2);

		 write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2);

		 write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2);

		 write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2);

	case 6:

	case 6:

		 write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2);

		 write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2);

	default:

	default:

		 write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2);

		 write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2);

	}

	}





	switch (max_lr_idx) {

	switch (max_lr_idx) {