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Commit fcbbe3da authored by Eric Yang's avatar Eric Yang Committed by Alex Deucher
Browse files

drm/amd/display: Use active + border for bw validation 



When doing SLS, KMD gives us clipped v_addressable with
border. This results in bw validation failure.

Signed-off-by: default avatarEric Yang <Eric.Yang2@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d596e5d0

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+5 −3
Original line number Diff line number Diff line
@@ -364,7 +364,8 @@ static void pipe_ctx_to_e2e_pipe_params ( 
	}





	input->dest.vactive        = pipe->stream->timing.v_addressable;

	input->dest.vactive        = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top

			+ pipe->stream->timing.v_border_bottom;



	input->dest.recout_width   = pipe->plane_res.scl_data.recout.width;

	input->dest.recout_height  = pipe->plane_res.scl_data.recout.height;
@@ -882,10 +883,11 @@ bool dcn_validate_bandwidth( 


		v->htotal[input_idx] = pipe->stream->timing.h_total;

		v->vtotal[input_idx] = pipe->stream->timing.v_total;

		v->vactive[input_idx] = pipe->stream->timing.v_addressable +

				pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;

		v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total

				- pipe->stream->timing.v_addressable

				- v->vactive[input_idx]

				- pipe->stream->timing.v_front_porch;

		v->vactive[input_idx] = pipe->stream->timing.v_addressable;

		v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f;



		if (!pipe->plane_state) {