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Commit fc77426a authored by Sagar Arun Kamble's avatar Sagar Arun Kamble Committed by Chris Wilson
Browse files

drm/i915: Create generic functions to control RC6, RPS 



Prepared generic functions intel_enable_rc6, intel_disable_rc6,
intel_enable_rps and intel_disable_rps functions to setup RC6/RPS
based on platforms.

v2: Make intel_enable/disable_rc6/rps static. (Chris)

v3: Added lockdep_assert_held(dev_priv->pcu_lock) in new generic
functions. (Chris)
Removed WARN_ON(&dev_priv->pcu_lock) from lower level functions as generic
function now has lockdep_assert. Rebase.

Signed-off-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-12-git-send-email-sagar.a.kamble@intel.com


Acked-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010213010.7415-11-chris@chris-wilson.co.uk
parent 0870a2a4

drivers/gpu/drm/i915/intel_pm.c

+70 −46
Original line number Diff line number Diff line
@@ -6731,8 +6731,6 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv) 
	int rc6_mode;

	int ret;



	WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));



	I915_WRITE(GEN6_RC_STATE, 0);



	/* Clear the DBG now so we don't confuse earlier errors */
@@ -6805,8 +6803,6 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv) 


static void gen6_enable_rps(struct drm_i915_private *dev_priv)

{

	WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));



	/* Here begins a magic sequence of register writes to enable

	 * auto-downclocking.

	 *
@@ -7227,8 +7223,6 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv) 
	enum intel_engine_id id;

	u32 gtfifodbg, rc6_mode = 0, pcbr;



	WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));



	gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |

					     GT_FIFO_FREE_ENTRIES_CHV);

	if (gtfifodbg) {
@@ -7281,8 +7275,6 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv) 
{

	u32 val;



	WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));



	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);



	/* 1: Program defaults and thresholds for RPS*/
@@ -7327,8 +7319,6 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv) 
	enum intel_engine_id id;

	u32 gtfifodbg, rc6_mode = 0;



	WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));



	valleyview_check_pctx(dev_priv);



	gtfifodbg = I915_READ(GTFIFODBG);
@@ -7374,8 +7364,6 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) 
{

	u32 val;



	WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));



	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);



	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
@@ -7989,31 +7977,47 @@ static inline void intel_disable_llc_pstate(struct drm_i915_private *i915) 
	/* Currently there is no HW configuration to be done to disable. */

}



void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)

static void intel_disable_rc6(struct drm_i915_private *dev_priv)

{

	struct intel_rps *rps = &dev_priv->gt_pm.rps;

	lockdep_assert_held(&dev_priv->pcu_lock);



	if (!READ_ONCE(rps->enabled))

		return;

	if (INTEL_GEN(dev_priv) >= 9)

		gen9_disable_rc6(dev_priv);

	else if (IS_CHERRYVIEW(dev_priv))

		cherryview_disable_rc6(dev_priv);

	else if (IS_VALLEYVIEW(dev_priv))

		valleyview_disable_rc6(dev_priv);

	else if (INTEL_GEN(dev_priv) >= 6)

		gen6_disable_rc6(dev_priv);

}



	mutex_lock(&dev_priv->pcu_lock);

static void intel_disable_rps(struct drm_i915_private *dev_priv)

{

	lockdep_assert_held(&dev_priv->pcu_lock);



	if (INTEL_GEN(dev_priv) >= 9) {

		gen9_disable_rc6(dev_priv);

	if (INTEL_GEN(dev_priv) >= 9)

		gen9_disable_rps(dev_priv);

	} else if (IS_CHERRYVIEW(dev_priv)) {

		cherryview_disable_rc6(dev_priv);

	else if (IS_CHERRYVIEW(dev_priv))

		cherryview_disable_rps(dev_priv);

	} else if (IS_VALLEYVIEW(dev_priv)) {

		valleyview_disable_rc6(dev_priv);

	else if (IS_VALLEYVIEW(dev_priv))

		valleyview_disable_rps(dev_priv);

	} else if (INTEL_GEN(dev_priv) >= 6) {

		gen6_disable_rc6(dev_priv);

	else if (INTEL_GEN(dev_priv) >= 6)

		gen6_disable_rps(dev_priv);

	}  else if (IS_IRONLAKE_M(dev_priv)) {

	else if (IS_IRONLAKE_M(dev_priv))

		ironlake_disable_drps(dev_priv);

}



void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)

{

	struct intel_rps *rps = &dev_priv->gt_pm.rps;



	if (!READ_ONCE(rps->enabled))

		return;



	mutex_lock(&dev_priv->pcu_lock);



	intel_disable_rc6(dev_priv);

	intel_disable_rps(dev_priv);

	if (HAS_LLC(dev_priv))

		intel_disable_llc_pstate(dev_priv);
@@ -8028,50 +8032,70 @@ static inline void intel_enable_llc_pstate(struct drm_i915_private *i915) 
	gen6_update_ring_freq(i915);

}



void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)

static void intel_enable_rc6(struct drm_i915_private *dev_priv)

{

	struct intel_rps *rps = &dev_priv->gt_pm.rps;

	lockdep_assert_held(&dev_priv->pcu_lock);



	/* We shouldn't be disabling as we submit, so this should be less

	 * racy than it appears!

	 */

	if (READ_ONCE(rps->enabled))

		return;

	if (IS_CHERRYVIEW(dev_priv))

		cherryview_enable_rc6(dev_priv);

	else if (IS_VALLEYVIEW(dev_priv))

		valleyview_enable_rc6(dev_priv);

	else if (INTEL_GEN(dev_priv) >= 9)

		gen9_enable_rc6(dev_priv);

	else if (IS_BROADWELL(dev_priv))

		gen8_enable_rc6(dev_priv);

	else if (INTEL_GEN(dev_priv) >= 6)

		gen6_enable_rc6(dev_priv);

}



	/* Powersaving is controlled by the host when inside a VM */

	if (intel_vgpu_active(dev_priv))

		return;

static void intel_enable_rps(struct drm_i915_private *dev_priv)

{

	struct intel_rps *rps = &dev_priv->gt_pm.rps;



	mutex_lock(&dev_priv->pcu_lock);

	lockdep_assert_held(&dev_priv->pcu_lock);



	if (IS_CHERRYVIEW(dev_priv)) {

		cherryview_enable_rc6(dev_priv);

		cherryview_enable_rps(dev_priv);

	} else if (IS_VALLEYVIEW(dev_priv)) {

		valleyview_enable_rc6(dev_priv);

		valleyview_enable_rps(dev_priv);

	} else if (INTEL_GEN(dev_priv) >= 9) {

		gen9_enable_rc6(dev_priv);

		gen9_enable_rps(dev_priv);

	} else if (IS_BROADWELL(dev_priv)) {

		gen8_enable_rc6(dev_priv);

		gen8_enable_rps(dev_priv);

	} else if (INTEL_GEN(dev_priv) >= 6) {

		gen6_enable_rc6(dev_priv);

		gen6_enable_rps(dev_priv);

	} else if (IS_IRONLAKE_M(dev_priv)) {

		ironlake_enable_drps(dev_priv);

		intel_init_emon(dev_priv);

	}



	if (HAS_LLC(dev_priv))

		intel_enable_llc_pstate(dev_priv);



	WARN_ON(rps->max_freq < rps->min_freq);

	WARN_ON(rps->idle_freq > rps->max_freq);



	WARN_ON(rps->efficient_freq < rps->min_freq);

	WARN_ON(rps->efficient_freq > rps->max_freq);

}



void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)

{

	struct intel_rps *rps = &dev_priv->gt_pm.rps;



	/* We shouldn't be disabling as we submit, so this should be less

	 * racy than it appears!

	 */

	if (READ_ONCE(rps->enabled))

		return;



	/* Powersaving is controlled by the host when inside a VM */

	if (intel_vgpu_active(dev_priv))

		return;



	mutex_lock(&dev_priv->pcu_lock);



	intel_enable_rc6(dev_priv);

	intel_enable_rps(dev_priv);

	if (HAS_LLC(dev_priv))

		intel_enable_llc_pstate(dev_priv);



	rps->enabled = true;

	mutex_unlock(&dev_priv->pcu_lock);