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Commit fc2834a4 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-dt-for-v4.6' of... 

Merge tag 'renesas-dt-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM Based SoC DT Updates for v4.6

* Use SCIF and USBHS fallback compatibility strings
* Add Baud Rate Generator (BRG) support for (H)SCIF
* Enable SCIF_CLK frequency and pins
* Use GIC_* defines
* Enable audio on r8a7793/gose
* Enable HDMI vidio out on r8a7793
* Enable i2c on r8a7793/gose
* Enable QSPI on alt
* Enable GPIO keys and leds on gise
* Enable audio on porter
* Enable DU on porter

* tag 'renesas-dt-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

: (68 commits)
  ARM: dts: silk: Enable SCIF_CLK frequency and pins
  ARM: dts: porter: Enable SCIF_CLK frequency and pins
  ARM: dts: marzen: Enable SCIF_CLK frequency and pins
  ARM: dts: lager: Enable SCIF_CLK frequency and pins
  ARM: dts: koelsch: Enable SCIF_CLK frequency and pins
  ARM: dts: gose: Enable SCIF_CLK frequency and pins
  ARM: dts: bockw: Enable SCIF_CLK frequency and pins
  ARM: dts: alt: Enable SCIF_CLK frequency and pins
  ARM: dts: r8a7794: Add BRG support for (H)SCIF
  ARM: dts: r8a7793: Add BRG support for SCIF
  ARM: dts: r8a7791: Add BRG support for (H)SCIF
  ARM: dts: r8a7790: Add BRG support for (H)SCIF
  ARM: dts: r8a7779: Add BRG support for SCIF
  ARM: dts: r8a7778: Add BRG support for SCIF
  ARM: dts: r8a7794: Rename the serial port clock to fck
  ARM: dts: r8a7793: Rename the serial port clock to fck
  ARM: dts: r8a7791: Rename the serial port clock to fck
  ARM: dts: r8a7790: Rename the serial port clock to fck
  ARM: dts: r8a7779: Rename the serial port clock to fck
  ARM: dts: r8a7778: Rename the serial port clock to fck
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents f68a4535 c3373b09

arch/arm/boot/dts/emev2.dtsi

+20 −19
Original line number Original line Diff line number Diff line
@@ -9,6 +9,7 @@ 
 */

 */





#include "skeleton.dtsi"

#include "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/irq.h>





/ {

/ {
@@ -53,8 +54,8 @@ 




	pmu {

	pmu {

		compatible = "arm,cortex-a9-pmu";

		compatible = "arm,cortex-a9-pmu";

		interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

			     <0 121 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

	};

	};





	clocks@e0110000 {

	clocks@e0110000 {
@@ -158,7 +159,7 @@ 
	timer@e0180000 {

	timer@e0180000 {

		compatible = "renesas,em-sti";

		compatible = "renesas,em-sti";

		reg = <0xe0180000 0x54>;

		reg = <0xe0180000 0x54>;

		interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&sti_sclk>;

		clocks = <&sti_sclk>;

		clock-names = "sclk";

		clock-names = "sclk";

	};

	};
@@ -166,7 +167,7 @@ 
	uart0: serial@e1020000 {

	uart0: serial@e1020000 {

		compatible = "renesas,em-uart";

		compatible = "renesas,em-uart";

		reg = <0xe1020000 0x38>;

		reg = <0xe1020000 0x38>;

		interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&usia_u0_sclk>;

		clocks = <&usia_u0_sclk>;

		clock-names = "sclk";

		clock-names = "sclk";

	};

	};
@@ -174,7 +175,7 @@ 
	uart1: serial@e1030000 {

	uart1: serial@e1030000 {

		compatible = "renesas,em-uart";

		compatible = "renesas,em-uart";

		reg = <0xe1030000 0x38>;

		reg = <0xe1030000 0x38>;

		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&usib_u1_sclk>;

		clocks = <&usib_u1_sclk>;

		clock-names = "sclk";

		clock-names = "sclk";

	};

	};
@@ -182,7 +183,7 @@ 
	uart2: serial@e1040000 {

	uart2: serial@e1040000 {

		compatible = "renesas,em-uart";

		compatible = "renesas,em-uart";

		reg = <0xe1040000 0x38>;

		reg = <0xe1040000 0x38>;

		interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&usib_u2_sclk>;

		clocks = <&usib_u2_sclk>;

		clock-names = "sclk";

		clock-names = "sclk";

	};

	};
@@ -190,7 +191,7 @@ 
	uart3: serial@e1050000 {

	uart3: serial@e1050000 {

		compatible = "renesas,em-uart";

		compatible = "renesas,em-uart";

		reg = <0xe1050000 0x38>;

		reg = <0xe1050000 0x38>;

		interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&usib_u3_sclk>;

		clocks = <&usib_u3_sclk>;

		clock-names = "sclk";

		clock-names = "sclk";

	};

	};
@@ -203,8 +204,8 @@ 
	gpio0: gpio@e0050000 {

	gpio0: gpio@e0050000 {

		compatible = "renesas,em-gio";

		compatible = "renesas,em-gio";

		reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;

		reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;

		interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,

			     <0 68 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		gpio-controller;

		gpio-ranges = <&pfc 0 0 32>;

		gpio-ranges = <&pfc 0 0 32>;

		#gpio-cells = <2>;

		#gpio-cells = <2>;
@@ -215,8 +216,8 @@ 
	gpio1: gpio@e0050080 {

	gpio1: gpio@e0050080 {

		compatible = "renesas,em-gio";

		compatible = "renesas,em-gio";

		reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;

		reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;

		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

			     <0 70 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		gpio-controller;

		gpio-ranges = <&pfc 0 32 32>;

		gpio-ranges = <&pfc 0 32 32>;

		#gpio-cells = <2>;

		#gpio-cells = <2>;
@@ -227,8 +228,8 @@ 
	gpio2: gpio@e0050100 {

	gpio2: gpio@e0050100 {

		compatible = "renesas,em-gio";

		compatible = "renesas,em-gio";

		reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;

		reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;

		interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,

			     <0 72 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		gpio-controller;

		gpio-ranges = <&pfc 0 64 32>;

		gpio-ranges = <&pfc 0 64 32>;

		#gpio-cells = <2>;

		#gpio-cells = <2>;
@@ -239,8 +240,8 @@ 
	gpio3: gpio@e0050180 {

	gpio3: gpio@e0050180 {

		compatible = "renesas,em-gio";

		compatible = "renesas,em-gio";

		reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;

		reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;

		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,

			     <0 74 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		gpio-controller;

		gpio-ranges = <&pfc 0 96 32>;

		gpio-ranges = <&pfc 0 96 32>;

		#gpio-cells = <2>;

		#gpio-cells = <2>;
@@ -251,8 +252,8 @@ 
	gpio4: gpio@e0050200 {

	gpio4: gpio@e0050200 {

		compatible = "renesas,em-gio";

		compatible = "renesas,em-gio";

		reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;

		reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;

		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,

			     <0 76 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		gpio-controller;

		gpio-ranges = <&pfc 0 128 31>;

		gpio-ranges = <&pfc 0 128 31>;

		#gpio-cells = <2>;

		#gpio-cells = <2>;
@@ -266,7 +267,7 @@ 
		#size-cells = <0>;

		#size-cells = <0>;

		compatible = "renesas,iic-emev2";

		compatible = "renesas,iic-emev2";

		reg = <0xe0070000 0x28>;

		reg = <0xe0070000 0x28>;

		interrupts = <0 32 IRQ_TYPE_EDGE_RISING>;

		interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;

		clocks = <&iic0_sclk>;

		clocks = <&iic0_sclk>;

		clock-names = "sclk";

		clock-names = "sclk";

		status = "disabled";

		status = "disabled";
@@ -277,7 +278,7 @@ 
		#size-cells = <0>;

		#size-cells = <0>;

		compatible = "renesas,iic-emev2";

		compatible = "renesas,iic-emev2";

		reg = <0xe10a0000 0x28>;

		reg = <0xe10a0000 0x28>;

		interrupts = <0 33 IRQ_TYPE_EDGE_RISING>;

		interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;

		clocks = <&iic1_sclk>;

		clocks = <&iic1_sclk>;

		clock-names = "sclk";

		clock-names = "sclk";

		status = "disabled";

		status = "disabled";

arch/arm/boot/dts/r7s72100.dtsi

+89 −88
Original line number Original line Diff line number Diff line
@@ -10,6 +10,7 @@ 
 */

 */





#include <dt-bindings/clock/r7s72100-clock.h>

#include <dt-bindings/clock/r7s72100-clock.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/irq.h>





/ {

/ {
@@ -152,12 +153,12 @@ 
	scif0: serial@e8007000 {

	scif0: serial@e8007000 {

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		reg = <0xe8007000 64>;

		reg = <0xe8007000 64>;

		interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

			     <0 191 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,

			     <0 192 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,

			     <0 189 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -165,12 +166,12 @@ 
	scif1: serial@e8007800 {

	scif1: serial@e8007800 {

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		reg = <0xe8007800 64>;

		reg = <0xe8007800 64>;

		interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,

			     <0 195 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,

			     <0 196 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,

			     <0 193 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -178,12 +179,12 @@ 
	scif2: serial@e8008000 {

	scif2: serial@e8008000 {

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		reg = <0xe8008000 64>;

		reg = <0xe8008000 64>;

		interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,

			     <0 199 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,

			     <0 200 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,

			     <0 197 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -191,12 +192,12 @@ 
	scif3: serial@e8008800 {

	scif3: serial@e8008800 {

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		reg = <0xe8008800 64>;

		reg = <0xe8008800 64>;

		interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,

			     <0 203 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,

			     <0 204 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,

			     <0 201 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -204,12 +205,12 @@ 
	scif4: serial@e8009000 {

	scif4: serial@e8009000 {

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		reg = <0xe8009000 64>;

		reg = <0xe8009000 64>;

		interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,

			     <0 207 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,

			     <0 208 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,

			     <0 205 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -217,12 +218,12 @@ 
	scif5: serial@e8009800 {

	scif5: serial@e8009800 {

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		reg = <0xe8009800 64>;

		reg = <0xe8009800 64>;

		interrupts = <0 210 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,

			     <0 211 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,

			     <0 212 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,

			     <0 209 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -230,12 +231,12 @@ 
	scif6: serial@e800a000 {

	scif6: serial@e800a000 {

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		reg = <0xe800a000 64>;

		reg = <0xe800a000 64>;

		interrupts = <0 214 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,

			     <0 215 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,

			     <0 216 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,

			     <0 213 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -243,12 +244,12 @@ 
	scif7: serial@e800a800 {

	scif7: serial@e800a800 {

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		reg = <0xe800a800 64>;

		reg = <0xe800a800 64>;

		interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,

			     <0 219 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,

			     <0 220 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,

			     <0 217 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -256,9 +257,9 @@ 
	spi0: spi@e800c800 {

	spi0: spi@e800c800 {

		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";

		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";

		reg = <0xe800c800 0x24>;

		reg = <0xe800c800 0x24>;

		interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

			     <0 239 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,

			     <0 240 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI0>;

		clocks = <&mstp10_clks R7S72100_CLK_SPI0>;

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;
@@ -271,9 +272,9 @@ 
	spi1: spi@e800d000 {

	spi1: spi@e800d000 {

		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";

		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";

		reg = <0xe800d000 0x24>;

		reg = <0xe800d000 0x24>;

		interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,

			     <0 242 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,

			     <0 243 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI1>;

		clocks = <&mstp10_clks R7S72100_CLK_SPI1>;

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;
@@ -286,9 +287,9 @@ 
	spi2: spi@e800d800 {

	spi2: spi@e800d800 {

		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";

		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";

		reg = <0xe800d800 0x24>;

		reg = <0xe800d800 0x24>;

		interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,

			     <0 245 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,

			     <0 246 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI2>;

		clocks = <&mstp10_clks R7S72100_CLK_SPI2>;

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;
@@ -301,9 +302,9 @@ 
	spi3: spi@e800e000 {

	spi3: spi@e800e000 {

		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";

		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";

		reg = <0xe800e000 0x24>;

		reg = <0xe800e000 0x24>;

		interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,

			     <0 248 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,

			     <0 249 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI3>;

		clocks = <&mstp10_clks R7S72100_CLK_SPI3>;

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;
@@ -316,9 +317,9 @@ 
	spi4: spi@e800e800 {

	spi4: spi@e800e800 {

		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";

		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";

		reg = <0xe800e800 0x24>;

		reg = <0xe800e800 0x24>;

		interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,

			     <0 251 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,

			     <0 252 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI4>;

		clocks = <&mstp10_clks R7S72100_CLK_SPI4>;

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;
@@ -342,14 +343,14 @@ 
		#size-cells = <0>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfee000 0x44>;

		reg = <0xfcfee000 0x44>;

		interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,

			     <0 158 IRQ_TYPE_EDGE_RISING>,

			     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,

			     <0 159 IRQ_TYPE_EDGE_RISING>,

			     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,

			     <0 160 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,

			     <0 161 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,

			     <0 162 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,

			     <0 163 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

			     <0 164 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;

		clock-frequency = <100000>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;
@@ -361,14 +362,14 @@ 
		#size-cells = <0>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfee400 0x44>;

		reg = <0xfcfee400 0x44>;

		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,

			     <0 166 IRQ_TYPE_EDGE_RISING>,

			     <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,

			     <0 167 IRQ_TYPE_EDGE_RISING>,

			     <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,

			     <0 168 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

			     <0 169 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,

			     <0 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <0 171 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,

			     <0 172 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;

		clock-frequency = <100000>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;
@@ -380,14 +381,14 @@ 
		#size-cells = <0>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfee800 0x44>;

		reg = <0xfcfee800 0x44>;

		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,

			     <0 174 IRQ_TYPE_EDGE_RISING>,

			     <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,

			     <0 175 IRQ_TYPE_EDGE_RISING>,

			     <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,

			     <0 176 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,

			     <0 177 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,

			     <0 178 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,

			     <0 179 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,

			     <0 180 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;

		clock-frequency = <100000>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;
@@ -399,14 +400,14 @@ 
		#size-cells = <0>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfeec00 0x44>;

		reg = <0xfcfeec00 0x44>;

		interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,

		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

			     <0 182 IRQ_TYPE_EDGE_RISING>,

			     <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,

			     <0 183 IRQ_TYPE_EDGE_RISING>,

			     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,

			     <0 184 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

			     <0 185 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

			     <0 186 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

			     <0 187 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

			     <0 188 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;

		clock-frequency = <100000>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		power-domains = <&cpg_clocks>;
@@ -416,7 +417,7 @@ 
	mtu2: timer@fcff0000 {

	mtu2: timer@fcff0000 {

		compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";

		compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";

		reg = <0xfcff0000 0x400>;

		reg = <0xfcff0000 0x400>;

		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "tgi0a";

		interrupt-names = "tgi0a";

		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;

		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;

		clock-names = "fck";

		clock-names = "fck";

arch/arm/boot/dts/r8a73a4.dtsi

+112 −112

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/boot/dts/r8a7740.dtsi

+81 −80

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/boot/dts/r8a7778-bockw.dts

+13 −0
Original line number Original line Diff line number Diff line
@@ -126,11 +126,19 @@ 
};

};





&pfc {

&pfc {

	pinctrl-0 = <&scif_clk_pins>;

	pinctrl-names = "default";



	scif0_pins: serial0 {

	scif0_pins: serial0 {

		renesas,groups = "scif0_data_a", "scif0_ctrl";

		renesas,groups = "scif0_data_a", "scif0_ctrl";

		renesas,function = "scif0";

		renesas,function = "scif0";

	};

	};





	scif_clk_pins: scif_clk {

		renesas,groups = "scif_clk";

		renesas,function = "scif_clk";

	};



	mmc_pins: mmc {

	mmc_pins: mmc {

		renesas,groups = "mmc_data8", "mmc_ctrl";

		renesas,groups = "mmc_data8", "mmc_ctrl";

		renesas,function = "mmc";

		renesas,function = "mmc";
@@ -217,3 +225,8 @@ 




	status = "okay";

	status = "okay";

};

};



&scif_clk {

	clock-frequency = <14745600>;

	status = "okay";

};