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Commit fc095690 authored by Tony Cheng's avatar Tony Cheng Committed by Alex Deucher
Browse files

drm/amd/display: register programming consolidation 



remove redundant DPP_CLOCK_ENABLE in ipp. clock programmed by HWSS

Signed-off-by: default avatarTony Cheng <tony.cheng@amd.com>
Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 72f0281d

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c

+0 −1
Original line number Diff line number Diff line
@@ -418,7 +418,6 @@ static void ippn10_enable_cm_block( 
{

	struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);



	REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);

	REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);

}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h

+0 −2
Original line number Diff line number Diff line
@@ -235,7 +235,6 @@ 
	IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \

	IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \

	IPP_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \

	IPP_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \

	IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \

	IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \

	IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \
@@ -433,7 +432,6 @@ 
	type CM_DGAM_LUT_WRITE_SEL; \

	type CM_DGAM_LUT_INDEX; \

	type CM_DGAM_LUT_DATA; \

	type DPP_CLOCK_ENABLE; \

	type CM_BYPASS_EN; \

	type CM_BYPASS; \

	type CNVC_SURFACE_PIXEL_FORMAT; \