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Commit fbe5c580 authored by Mark Brown's avatar Mark Brown
Browse files

ASoC: Update regmap access for WM5100 DSP control registers 



Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent c97f3bdd

sound/soc/codecs/wm5100-tables.c

+123 −2
Original line number Diff line number Diff line
@@ -32,6 +32,17 @@ bool wm5100_volatile_register(struct device *dev, unsigned int reg) 
	case WM5100_MIC_DETECT_3:

		return 1;

	default:

		if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) ||

		    (reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) ||

		    (reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) ||

		    (reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) ||

		    (reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) ||

		    (reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) ||

		    (reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) ||

		    (reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) ||

		    (reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511))

			return 1;

		else

			return 0;

	}

}
@@ -697,8 +708,109 @@ bool wm5100_readable_register(struct device *dev, unsigned int reg) 
	case WM5100_HPLPF3_2:

	case WM5100_HPLPF4_1:

	case WM5100_HPLPF4_2:

	case WM5100_DSP1_CONTROL_1:

	case WM5100_DSP1_CONTROL_2:

	case WM5100_DSP1_CONTROL_3:

	case WM5100_DSP1_CONTROL_4:

	case WM5100_DSP1_CONTROL_5:

	case WM5100_DSP1_CONTROL_6:

	case WM5100_DSP1_CONTROL_7:

	case WM5100_DSP1_CONTROL_8:

	case WM5100_DSP1_CONTROL_9:

	case WM5100_DSP1_CONTROL_10:

	case WM5100_DSP1_CONTROL_11:

	case WM5100_DSP1_CONTROL_12:

	case WM5100_DSP1_CONTROL_13:

	case WM5100_DSP1_CONTROL_14:

	case WM5100_DSP1_CONTROL_15:

	case WM5100_DSP1_CONTROL_16:

	case WM5100_DSP1_CONTROL_17:

	case WM5100_DSP1_CONTROL_18:

	case WM5100_DSP1_CONTROL_19:

	case WM5100_DSP1_CONTROL_20:

	case WM5100_DSP1_CONTROL_21:

	case WM5100_DSP1_CONTROL_22:

	case WM5100_DSP1_CONTROL_23:

	case WM5100_DSP1_CONTROL_24:

	case WM5100_DSP1_CONTROL_25:

	case WM5100_DSP1_CONTROL_26:

	case WM5100_DSP1_CONTROL_27:

	case WM5100_DSP1_CONTROL_28:

	case WM5100_DSP1_CONTROL_29:

	case WM5100_DSP1_CONTROL_30:

	case WM5100_DSP2_CONTROL_1:

	case WM5100_DSP2_CONTROL_2:

	case WM5100_DSP2_CONTROL_3:

	case WM5100_DSP2_CONTROL_4:

	case WM5100_DSP2_CONTROL_5:

	case WM5100_DSP2_CONTROL_6:

	case WM5100_DSP2_CONTROL_7:

	case WM5100_DSP2_CONTROL_8:

	case WM5100_DSP2_CONTROL_9:

	case WM5100_DSP2_CONTROL_10:

	case WM5100_DSP2_CONTROL_11:

	case WM5100_DSP2_CONTROL_12:

	case WM5100_DSP2_CONTROL_13:

	case WM5100_DSP2_CONTROL_14:

	case WM5100_DSP2_CONTROL_15:

	case WM5100_DSP2_CONTROL_16:

	case WM5100_DSP2_CONTROL_17:

	case WM5100_DSP2_CONTROL_18:

	case WM5100_DSP2_CONTROL_19:

	case WM5100_DSP2_CONTROL_20:

	case WM5100_DSP2_CONTROL_21:

	case WM5100_DSP2_CONTROL_22:

	case WM5100_DSP2_CONTROL_23:

	case WM5100_DSP2_CONTROL_24:

	case WM5100_DSP2_CONTROL_25:

	case WM5100_DSP2_CONTROL_26:

	case WM5100_DSP2_CONTROL_27:

	case WM5100_DSP2_CONTROL_28:

	case WM5100_DSP2_CONTROL_29:

	case WM5100_DSP2_CONTROL_30:

	case WM5100_DSP3_CONTROL_1:

	case WM5100_DSP3_CONTROL_2:

	case WM5100_DSP3_CONTROL_3:

	case WM5100_DSP3_CONTROL_4:

	case WM5100_DSP3_CONTROL_5:

	case WM5100_DSP3_CONTROL_6:

	case WM5100_DSP3_CONTROL_7:

	case WM5100_DSP3_CONTROL_8:

	case WM5100_DSP3_CONTROL_9:

	case WM5100_DSP3_CONTROL_10:

	case WM5100_DSP3_CONTROL_11:

	case WM5100_DSP3_CONTROL_12:

	case WM5100_DSP3_CONTROL_13:

	case WM5100_DSP3_CONTROL_14:

	case WM5100_DSP3_CONTROL_15:

	case WM5100_DSP3_CONTROL_16:

	case WM5100_DSP3_CONTROL_17:

	case WM5100_DSP3_CONTROL_18:

	case WM5100_DSP3_CONTROL_19:

	case WM5100_DSP3_CONTROL_20:

	case WM5100_DSP3_CONTROL_21:

	case WM5100_DSP3_CONTROL_22:

	case WM5100_DSP3_CONTROL_23:

	case WM5100_DSP3_CONTROL_24:

	case WM5100_DSP3_CONTROL_25:

	case WM5100_DSP3_CONTROL_26:

	case WM5100_DSP3_CONTROL_27:

	case WM5100_DSP3_CONTROL_28:

	case WM5100_DSP3_CONTROL_29:

	case WM5100_DSP3_CONTROL_30:

		return 1;

	default:

		if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) ||

		    (reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) ||

		    (reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) ||

		    (reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) ||

		    (reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) ||

		    (reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) ||

		    (reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) ||

		    (reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) ||

		    (reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511))

			return 1;

		else

			return 0;

	}

}
@@ -1361,4 +1473,13 @@ struct reg_default wm5100_reg_defaults[WM5100_REGISTER_COUNT] = { 
	{ 0x0EC9, 0x0000 },  /* R3785  - HPLPF3_2 */

	{ 0x0ECC, 0x0000 },  /* R3788  - HPLPF4_1 */

	{ 0x0ECD, 0x0000 },  /* R3789  - HPLPF4_2 */

	{ 0x0F02, 0x0000 },  /* R3842  - DSP1 Control 2 */

	{ 0x0F03, 0x0000 },  /* R3843  - DSP1 Control 3 */

	{ 0x0F04, 0x0000 },  /* R3844  - DSP1 Control 4 */

	{ 0x1002, 0x0000 },  /* R4098  - DSP2 Control 2 */

	{ 0x1003, 0x0000 },  /* R4099  - DSP2 Control 3 */

	{ 0x1004, 0x0000 },  /* R4100  - DSP2 Control 4 */

	{ 0x1102, 0x0000 },  /* R4354  - DSP3 Control 2 */

	{ 0x1103, 0x0000 },  /* R4355  - DSP3 Control 3 */

	{ 0x1104, 0x0000 },  /* R4356  - DSP3 Control 4 */

};

sound/soc/codecs/wm5100.h

+159 −0
Original line number Diff line number Diff line
@@ -709,6 +709,96 @@ int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack); 
#define WM5100_HPLPF3_2                         0xEC9

#define WM5100_HPLPF4_1                         0xECC

#define WM5100_HPLPF4_2                         0xECD

#define WM5100_DSP1_CONTROL_1                   0xF00

#define WM5100_DSP1_CONTROL_2                   0xF02

#define WM5100_DSP1_CONTROL_3                   0xF03

#define WM5100_DSP1_CONTROL_4                   0xF04

#define WM5100_DSP1_CONTROL_5                   0xF06

#define WM5100_DSP1_CONTROL_6                   0xF07

#define WM5100_DSP1_CONTROL_7                   0xF08

#define WM5100_DSP1_CONTROL_8                   0xF09

#define WM5100_DSP1_CONTROL_9                   0xF0A

#define WM5100_DSP1_CONTROL_10                  0xF0B

#define WM5100_DSP1_CONTROL_11                  0xF0C

#define WM5100_DSP1_CONTROL_12                  0xF0D

#define WM5100_DSP1_CONTROL_13                  0xF0F

#define WM5100_DSP1_CONTROL_14                  0xF10

#define WM5100_DSP1_CONTROL_15                  0xF11

#define WM5100_DSP1_CONTROL_16                  0xF12

#define WM5100_DSP1_CONTROL_17                  0xF13

#define WM5100_DSP1_CONTROL_18                  0xF14

#define WM5100_DSP1_CONTROL_19                  0xF16

#define WM5100_DSP1_CONTROL_20                  0xF17

#define WM5100_DSP1_CONTROL_21                  0xF18

#define WM5100_DSP1_CONTROL_22                  0xF1A

#define WM5100_DSP1_CONTROL_23                  0xF1B

#define WM5100_DSP1_CONTROL_24                  0xF1C

#define WM5100_DSP1_CONTROL_25                  0xF1E

#define WM5100_DSP1_CONTROL_26                  0xF20

#define WM5100_DSP1_CONTROL_27                  0xF21

#define WM5100_DSP1_CONTROL_28                  0xF22

#define WM5100_DSP1_CONTROL_29                  0xF23

#define WM5100_DSP1_CONTROL_30                  0xF24

#define WM5100_DSP2_CONTROL_1                   0x1000

#define WM5100_DSP2_CONTROL_2                   0x1002

#define WM5100_DSP2_CONTROL_3                   0x1003

#define WM5100_DSP2_CONTROL_4                   0x1004

#define WM5100_DSP2_CONTROL_5                   0x1006

#define WM5100_DSP2_CONTROL_6                   0x1007

#define WM5100_DSP2_CONTROL_7                   0x1008

#define WM5100_DSP2_CONTROL_8                   0x1009

#define WM5100_DSP2_CONTROL_9                   0x100A

#define WM5100_DSP2_CONTROL_10                  0x100B

#define WM5100_DSP2_CONTROL_11                  0x100C

#define WM5100_DSP2_CONTROL_12                  0x100D

#define WM5100_DSP2_CONTROL_13                  0x100F

#define WM5100_DSP2_CONTROL_14                  0x1010

#define WM5100_DSP2_CONTROL_15                  0x1011

#define WM5100_DSP2_CONTROL_16                  0x1012

#define WM5100_DSP2_CONTROL_17                  0x1013

#define WM5100_DSP2_CONTROL_18                  0x1014

#define WM5100_DSP2_CONTROL_19                  0x1016

#define WM5100_DSP2_CONTROL_20                  0x1017

#define WM5100_DSP2_CONTROL_21                  0x1018

#define WM5100_DSP2_CONTROL_22                  0x101A

#define WM5100_DSP2_CONTROL_23                  0x101B

#define WM5100_DSP2_CONTROL_24                  0x101C

#define WM5100_DSP2_CONTROL_25                  0x101E

#define WM5100_DSP2_CONTROL_26                  0x1020

#define WM5100_DSP2_CONTROL_27                  0x1021

#define WM5100_DSP2_CONTROL_28                  0x1022

#define WM5100_DSP2_CONTROL_29                  0x1023

#define WM5100_DSP2_CONTROL_30                  0x1024

#define WM5100_DSP3_CONTROL_1                   0x1100

#define WM5100_DSP3_CONTROL_2                   0x1102

#define WM5100_DSP3_CONTROL_3                   0x1103

#define WM5100_DSP3_CONTROL_4                   0x1104

#define WM5100_DSP3_CONTROL_5                   0x1106

#define WM5100_DSP3_CONTROL_6                   0x1107

#define WM5100_DSP3_CONTROL_7                   0x1108

#define WM5100_DSP3_CONTROL_8                   0x1109

#define WM5100_DSP3_CONTROL_9                   0x110A

#define WM5100_DSP3_CONTROL_10                  0x110B

#define WM5100_DSP3_CONTROL_11                  0x110C

#define WM5100_DSP3_CONTROL_12                  0x110D

#define WM5100_DSP3_CONTROL_13                  0x110F

#define WM5100_DSP3_CONTROL_14                  0x1110

#define WM5100_DSP3_CONTROL_15                  0x1111

#define WM5100_DSP3_CONTROL_16                  0x1112

#define WM5100_DSP3_CONTROL_17                  0x1113

#define WM5100_DSP3_CONTROL_18                  0x1114

#define WM5100_DSP3_CONTROL_19                  0x1116

#define WM5100_DSP3_CONTROL_20                  0x1117

#define WM5100_DSP3_CONTROL_21                  0x1118

#define WM5100_DSP3_CONTROL_22                  0x111A

#define WM5100_DSP3_CONTROL_23                  0x111B

#define WM5100_DSP3_CONTROL_24                  0x111C

#define WM5100_DSP3_CONTROL_25                  0x111E

#define WM5100_DSP3_CONTROL_26                  0x1120

#define WM5100_DSP3_CONTROL_27                  0x1121

#define WM5100_DSP3_CONTROL_28                  0x1122

#define WM5100_DSP3_CONTROL_29                  0x1123

#define WM5100_DSP3_CONTROL_30                  0x1124

#define WM5100_DSP1_DM_0                        0x4000

#define WM5100_DSP1_DM_1                        0x4001

#define WM5100_DSP1_DM_2                        0x4002
@@ -4560,6 +4650,75 @@ int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack); 
#define WM5100_LHPF4_COEFF_SHIFT                     0  /* LHPF4_COEFF - [15:0] */

#define WM5100_LHPF4_COEFF_WIDTH                    16  /* LHPF4_COEFF - [15:0] */



/*

 * R4132 (0x1024) - DSP2 Control 30

 */

#define WM5100_DSP2_RATE_MASK                   0xC000  /* DSP2_RATE - [15:14] */

#define WM5100_DSP2_RATE_SHIFT                      14  /* DSP2_RATE - [15:14] */

#define WM5100_DSP2_RATE_WIDTH                       2  /* DSP2_RATE - [15:14] */

#define WM5100_DSP2_DBG_CLK_ENA                 0x0008  /* DSP2_DBG_CLK_ENA */

#define WM5100_DSP2_DBG_CLK_ENA_MASK            0x0008  /* DSP2_DBG_CLK_ENA */

#define WM5100_DSP2_DBG_CLK_ENA_SHIFT                3  /* DSP2_DBG_CLK_ENA */

#define WM5100_DSP2_DBG_CLK_ENA_WIDTH                1  /* DSP2_DBG_CLK_ENA */

#define WM5100_DSP2_SYS_ENA                     0x0004  /* DSP2_SYS_ENA */

#define WM5100_DSP2_SYS_ENA_MASK                0x0004  /* DSP2_SYS_ENA */

#define WM5100_DSP2_SYS_ENA_SHIFT                    2  /* DSP2_SYS_ENA */

#define WM5100_DSP2_SYS_ENA_WIDTH                    1  /* DSP2_SYS_ENA */

#define WM5100_DSP2_CORE_ENA                    0x0002  /* DSP2_CORE_ENA */

#define WM5100_DSP2_CORE_ENA_MASK               0x0002  /* DSP2_CORE_ENA */

#define WM5100_DSP2_CORE_ENA_SHIFT                   1  /* DSP2_CORE_ENA */

#define WM5100_DSP2_CORE_ENA_WIDTH                   1  /* DSP2_CORE_ENA */

#define WM5100_DSP2_START                       0x0001  /* DSP2_START */

#define WM5100_DSP2_START_MASK                  0x0001  /* DSP2_START */

#define WM5100_DSP2_START_SHIFT                      0  /* DSP2_START */

#define WM5100_DSP2_START_WIDTH                      1  /* DSP2_START */



/*

 * R3876 (0xF24) - DSP1 Control 30

 */

#define WM5100_DSP1_RATE_MASK                   0xC000  /* DSP1_RATE - [15:14] */

#define WM5100_DSP1_RATE_SHIFT                      14  /* DSP1_RATE - [15:14] */

#define WM5100_DSP1_RATE_WIDTH                       2  /* DSP1_RATE - [15:14] */

#define WM5100_DSP1_DBG_CLK_ENA                 0x0008  /* DSP1_DBG_CLK_ENA */

#define WM5100_DSP1_DBG_CLK_ENA_MASK            0x0008  /* DSP1_DBG_CLK_ENA */

#define WM5100_DSP1_DBG_CLK_ENA_SHIFT                3  /* DSP1_DBG_CLK_ENA */

#define WM5100_DSP1_DBG_CLK_ENA_WIDTH                1  /* DSP1_DBG_CLK_ENA */

#define WM5100_DSP1_SYS_ENA                     0x0004  /* DSP1_SYS_ENA */

#define WM5100_DSP1_SYS_ENA_MASK                0x0004  /* DSP1_SYS_ENA */

#define WM5100_DSP1_SYS_ENA_SHIFT                    2  /* DSP1_SYS_ENA */

#define WM5100_DSP1_SYS_ENA_WIDTH                    1  /* DSP1_SYS_ENA */

#define WM5100_DSP1_CORE_ENA                    0x0002  /* DSP1_CORE_ENA */

#define WM5100_DSP1_CORE_ENA_MASK               0x0002  /* DSP1_CORE_ENA */

#define WM5100_DSP1_CORE_ENA_SHIFT                   1  /* DSP1_CORE_ENA */

#define WM5100_DSP1_CORE_ENA_WIDTH                   1  /* DSP1_CORE_ENA */

#define WM5100_DSP1_START                       0x0001  /* DSP1_START */

#define WM5100_DSP1_START_MASK                  0x0001  /* DSP1_START */

#define WM5100_DSP1_START_SHIFT                      0  /* DSP1_START */

#define WM5100_DSP1_START_WIDTH                      1  /* DSP1_START */



/*

 * R4388 (0x1124) - DSP3 Control 30

 */

#define WM5100_DSP3_RATE_MASK                   0xC000  /* DSP3_RATE - [15:14] */

#define WM5100_DSP3_RATE_SHIFT                      14  /* DSP3_RATE - [15:14] */

#define WM5100_DSP3_RATE_WIDTH                       2  /* DSP3_RATE - [15:14] */

#define WM5100_DSP3_DBG_CLK_ENA                 0x0008  /* DSP3_DBG_CLK_ENA */

#define WM5100_DSP3_DBG_CLK_ENA_MASK            0x0008  /* DSP3_DBG_CLK_ENA */

#define WM5100_DSP3_DBG_CLK_ENA_SHIFT                3  /* DSP3_DBG_CLK_ENA */

#define WM5100_DSP3_DBG_CLK_ENA_WIDTH                1  /* DSP3_DBG_CLK_ENA */

#define WM5100_DSP3_SYS_ENA                     0x0004  /* DSP3_SYS_ENA */

#define WM5100_DSP3_SYS_ENA_MASK                0x0004  /* DSP3_SYS_ENA */

#define WM5100_DSP3_SYS_ENA_SHIFT                    2  /* DSP3_SYS_ENA */

#define WM5100_DSP3_SYS_ENA_WIDTH                    1  /* DSP3_SYS_ENA */

#define WM5100_DSP3_CORE_ENA                    0x0002  /* DSP3_CORE_ENA */

#define WM5100_DSP3_CORE_ENA_MASK               0x0002  /* DSP3_CORE_ENA */

#define WM5100_DSP3_CORE_ENA_SHIFT                   1  /* DSP3_CORE_ENA */

#define WM5100_DSP3_CORE_ENA_WIDTH                   1  /* DSP3_CORE_ENA */

#define WM5100_DSP3_START                       0x0001  /* DSP3_START */

#define WM5100_DSP3_START_MASK                  0x0001  /* DSP3_START */

#define WM5100_DSP3_START_SHIFT                      0  /* DSP3_START */

#define WM5100_DSP3_START_WIDTH                      1  /* DSP3_START */



/*

 * R16384 (0x4000) - DSP1 DM 0

 */