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Commit fb44a5a8 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: vidc: Change watchdog interrupt status and mask to 0x8"

parents cb18ebb3 e0163b60

drivers/media/platform/msm/vidc/venus_hfi.c

+4 −5
Original line number Diff line number Diff line
@@ -1503,7 +1503,7 @@ static int __iface_cmdq_write(struct venus_hfi_device *device, void *pkt) 
		/* Consumer of cmdq prefers that we raise an interrupt */

		rc = 0;

		__write_register(device, VIDC_CPU_IC_SOFTINT,

				VIDC_CPU_IC_SOFTINT_H2A_SHFT);

				1 << VIDC_CPU_IC_SOFTINT_H2A_SHFT);

	}



	return rc;
@@ -1539,7 +1539,7 @@ static int __iface_msgq_read(struct venus_hfi_device *device, void *pkt) 
		__hal_sim_modify_msg_packet((u8 *)pkt, device);

		if (tx_req_is_set)

			__write_register(device, VIDC_CPU_IC_SOFTINT,

				VIDC_CPU_IC_SOFTINT_H2A_SHFT);

					1 << VIDC_CPU_IC_SOFTINT_H2A_SHFT);

		rc = 0;

	} else

		rc = -ENODATA;
@@ -1571,7 +1571,7 @@ static int __iface_dbgq_read(struct venus_hfi_device *device, void *pkt) 
	if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {

		if (tx_req_is_set)

			__write_register(device, VIDC_CPU_IC_SOFTINT,

				VIDC_CPU_IC_SOFTINT_H2A_SHFT);

					1 << VIDC_CPU_IC_SOFTINT_H2A_SHFT);

		rc = 0;

	} else

		rc = -ENODATA;
@@ -2268,7 +2268,6 @@ static void __core_clear_interrupt(struct venus_hfi_device *device) 
	}



	__write_register(device, VIDC_CPU_CS_A2HSOFTINTCLR, 1);

	__write_register(device, VIDC_WRAPPER_INTR_CLEAR, intr_status);

}



static int venus_hfi_core_ping(void *device)
@@ -3430,7 +3429,7 @@ static int __response_handler(struct venus_hfi_device *device) 
		return 0;

	}



	if (device->intr_status & VIDC_WRAPPER_INTR_CLEAR_A2HWD_BMSK) {

	if (device->intr_status & VIDC_WRAPPER_INTR_STATUS_A2HWD_BMSK) {

		struct hfi_sfr_struct *vsfr = (struct hfi_sfr_struct *)

			device->sfr.align_virtual_addr;

		struct msm_vidc_cb_info info = {

drivers/media/platform/msm/vidc/vidc_hfi_io.h

+9 −23
Original line number Diff line number Diff line
@@ -16,8 +16,6 @@ 
#define VIDC_CPU_CS_BASE_OFFS		(VIDC_CPU_BASE_OFFS)

#define VIDC_CPU_IC_BASE_OFFS		(VIDC_CPU_BASE_OFFS)



#define VIDC_CPU_CS_REMAP_OFFS		(VIDC_CPU_CS_BASE_OFFS + 0x00)

#define VIDC_CPU_CS_TIMER_CONTROL	(VIDC_CPU_CS_BASE_OFFS + 0x04)

#define VIDC_CPU_CS_A2HSOFTINTEN	(VIDC_CPU_CS_BASE_OFFS + 0x10)

#define VIDC_CPU_CS_A2HSOFTINTENCLR	(VIDC_CPU_CS_BASE_OFFS + 0x14)

#define VIDC_CPU_CS_A2HSOFTINT		(VIDC_CPU_CS_BASE_OFFS + 0x18)
@@ -63,16 +61,10 @@ 


#define VIDC_CPU_CS_SCIBARG3		(VIDC_CPU_CS_BASE_OFFS + 0x6C)



#define VIDC_CPU_IC_IRQSTATUS		(VIDC_CPU_IC_BASE_OFFS + 0x00)

#define VIDC_CPU_IC_FIQSTATUS		(VIDC_CPU_IC_BASE_OFFS + 0x04)

#define VIDC_CPU_IC_RAWINTR			(VIDC_CPU_IC_BASE_OFFS + 0x08)

#define VIDC_CPU_IC_INTSELECT		(VIDC_CPU_IC_BASE_OFFS + 0x0C)

#define VIDC_CPU_IC_INTENABLE		(VIDC_CPU_IC_BASE_OFFS + 0x10)

#define VIDC_CPU_IC_INTENACLEAR		(VIDC_CPU_IC_BASE_OFFS + 0x14)

#define VIDC_CPU_IC_SOFTINT		(VIDC_CPU_IC_BASE_OFFS + 0x150)

#define VIDC_CPU_IC_SOFTINT_H2A_BMSK	0x8000

#define VIDC_CPU_IC_SOFTINT_H2A_SHFT	0x1

#define VIDC_CPU_IC_SOFTINTCLEAR	(VIDC_CPU_IC_BASE_OFFS + 0x1C)

#define VIDC_CPU_IC_SOFTINT_H2A_BMSK	0x1

#define VIDC_CPU_IC_SOFTINT_H2A_SHFT	0x0

#define VIDC_CPU_IC_SOFTINTCLEAR	(VIDC_CPU_IC_BASE_OFFS + 0x154)



/*

 * --------------------------------------------------------------------------
@@ -90,24 +82,18 @@ 
#define VIDC_WRAPPER_CLOCK_CONFIG	(VIDC_WRAPPER_BASE_OFFS + 0x04)



#define VIDC_WRAPPER_INTR_STATUS	(VIDC_WRAPPER_BASE_OFFS + 0x0C)

#define VIDC_WRAPPER_INTR_STATUS_A2HWD_BMSK	0x10

#define VIDC_WRAPPER_INTR_STATUS_A2HWD_SHFT	0x4

#define VIDC_WRAPPER_INTR_STATUS_A2HWD_BMSK	0x8

#define VIDC_WRAPPER_INTR_STATUS_A2HWD_SHFT	0x3

#define VIDC_WRAPPER_INTR_STATUS_A2H_BMSK	0x4

#define VIDC_WRAPPER_INTR_STATUS_A2H_SHFT	0x2



#define VIDC_WRAPPER_INTR_MASK		(VIDC_WRAPPER_BASE_OFFS + 0x10)

#define VIDC_WRAPPER_INTR_MASK_A2HWD_BMSK	0x10

#define VIDC_WRAPPER_INTR_MASK_A2HWD_SHFT	0x4

#define VIDC_WRAPPER_INTR_MASK_A2HWD_BMSK	0x8

#define VIDC_WRAPPER_INTR_MASK_A2HWD_SHFT	0x3

#define VIDC_WRAPPER_INTR_MASK_A2HVCODEC_BMSK	0x8

#define VIDC_WRAPPER_INTR_MASK_A2HCPU_BMSK	0x4

#define VIDC_WRAPPER_INTR_MASK_A2HCPU_SHFT	0x2



#define VIDC_WRAPPER_INTR_CLEAR		(VIDC_WRAPPER_BASE_OFFS + 0x14)

#define VIDC_WRAPPER_INTR_CLEAR_A2HWD_BMSK	0x10

#define VIDC_WRAPPER_INTR_CLEAR_A2HWD_SHFT	0x4

#define VIDC_WRAPPER_INTR_CLEAR_A2H_BMSK	0x4

#define VIDC_WRAPPER_INTR_CLEAR_A2H_SHFT	0x2



#define VIDC_WRAPPER_CPU_CLOCK_CONFIG	(VIDC_WRAPPER_BASE_OFFS + 0x2000)

#define VIDC_WRAPPER_CPU_CGC_DIS	(VIDC_WRAPPER_BASE_OFFS + 0x2010)

#define VIDC_WRAPPER_CPU_STATUS	(VIDC_WRAPPER_BASE_OFFS + 0x2014)