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Commit fae9eff5 authored by Wenjun Zhang's avatar Wenjun Zhang Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: re-calculate phy-timing for r66451 display panel 

Re-calculate phy-timing for r66451 display panel.

Change-Id: Ia5438346767e277bcffe8049d5ec5c65bdf4345d
parent 5a298b18

qcom/lagoon-sde-display.dtsi

+26 −26
Original line number Diff line number Diff line
@@ -245,12 +245,12 @@ 


&dsi_r66451_amoled_60hz_video {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-t-clk-post = <0x09>;

	qcom,mdss-dsi-t-clk-pre = <0x1B>;

	qcom,mdss-dsi-t-clk-post = <0x0A>;

	qcom,mdss-dsi-t-clk-pre = <0x1D>;

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 0F 03 03 1E 1D 04

				04 02 02 04 00];

			qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04

				04 03 02 04 00];

			qcom,display-topology = <1 1 1>;

			qcom,default-topology-index = <0>;

		};
@@ -260,11 +260,11 @@ 
&dsi_r66451_amoled_90hz_video {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-t-clk-post = <0x0B>;

	qcom,mdss-dsi-t-clk-pre = <0x21>;

	qcom,mdss-dsi-t-clk-pre = <0x27>;

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05

				05 03 02 04 00];

			qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06

				06 06 02 04 00];

			qcom,display-topology = <1 1 1>;

			qcom,default-topology-index = <0>;

		};
@@ -273,8 +273,8 @@ 


&dsi_r66451_amoled_120hz_video {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-t-clk-post = <0x0C>;

	qcom,mdss-dsi-t-clk-pre = <0x29>;

	qcom,mdss-dsi-t-clk-post = <0x0D>;

	qcom,mdss-dsi-t-clk-pre = <0x32>;

	qcom,dsi-supported-dfps-list = <120 90 60>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
@@ -282,8 +282,8 @@ 
	qcom,mdss-dsi-max-refresh-rate = <120>;

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07

				06 04 02 04 00];

			qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08

				08 08 02 04 00];

			qcom,display-topology = <1 1 1>;

			qcom,default-topology-index = <0>;

		};
@@ -292,12 +292,12 @@ 


&dsi_r66451_amoled_60hz_cmd {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-t-clk-post = <0x09>;

	qcom,mdss-dsi-t-clk-pre = <0x1B>;

	qcom,mdss-dsi-t-clk-post = <0x0A>;

	qcom,mdss-dsi-t-clk-pre = <0x1D>;

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 0F 03 03 1E 1D 04

				04 02 02 04 00];

			qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04

				04 03 02 04 00];

			qcom,display-topology = <1 1 1>;

			qcom,default-topology-index = <0>;

		};
@@ -307,11 +307,11 @@ 
&dsi_r66451_amoled_90hz_cmd {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-t-clk-post = <0x0B>;

	qcom,mdss-dsi-t-clk-pre = <0x21>;

	qcom,mdss-dsi-t-clk-pre = <0x27>;

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05

				05 03 02 04 00];

			qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06

				06 06 02 04 00];

			qcom,display-topology = <1 1 1>;

			qcom,default-topology-index = <0>;

		};
@@ -320,26 +320,26 @@ 


&dsi_r66451_amoled_120hz_cmd {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-t-clk-post = <0x0C>;

	qcom,mdss-dsi-t-clk-pre = <0x28>;

	qcom,mdss-dsi-t-clk-post = <0x0D>;

	qcom,mdss-dsi-t-clk-pre = <0x30>;

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 07

				06 04 02 04 00];

			qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07

				07 08 02 04 00];

			qcom,display-topology = <1 1 1>;

			qcom,default-topology-index = <0>;

		};



		timing@1 {

			qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05

				05 03 02 04 00];

			qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06

				06 06 02 04 00];

			qcom,display-topology = <1 1 1>;

			qcom,default-topology-index = <0>;

		};



		timing@2 {

			qcom,mdss-dsi-panel-phy-timings = [00 0F 03 03 1E 1D 04

				04 02 02 04 00];

			qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04

				04 03 02 04 00];

			qcom,display-topology = <1 1 1>;

			qcom,default-topology-index = <0>;

		};