Merge "ARM: dts: msm: add GDSC devices for KONA" (fad60cc4) · Commits · e / devices / android_kernel_oneplus_sm7250

arch/arm64/boot/dts/qcom/kona-rumi.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -26,7 +26,7 @@
		limit-tx-hs-gear = <1>;
		limit-rx-hs-gear = <1>;

		vdd-hba-supply = <&pm8150_s4>;
		vdd-hba-supply = <&ufs_phy_gdsc>;
		vdd-hba-fixed-regulator;
		vcc-supply = <&pm8150_l17>;
		vccq2-supply = <&pm8150_s4>;

arch/arm64/boot/dts/qcom/kona.dtsi

+238 −0

Original line number	Diff line number	Diff line
		@@ -595,6 +595,244 @@
		#clock-cells = <1>;
		};

		/* GCC GDSCs */
		pcie_0_gdsc: qcom,gdsc@16b004 {
		compatible = "qcom,gdsc";
		reg = <0x16b004 0x4>;
		regulator-name = "pcie_0_gdsc";
		};

		pcie_1_gdsc: qcom,gdsc@18d004 {
		compatible = "qcom,gdsc";
		reg = <0x18d004 0x4>;
		regulator-name = "pcie_1_gdsc";
		};

		pcie_2_gdsc: qcom,gdsc@106004 {
		compatible = "qcom,gdsc";
		reg = <0x106004 0x4>;
		regulator-name = "pcie_2_gdsc";
		};

		ufs_card_gdsc: qcom,gdsc@175004 {
		compatible = "qcom,gdsc";
		reg = <0x175004 0x4>;
		regulator-name = "ufs_card_gdsc";
		};

		ufs_phy_gdsc: qcom,gdsc@177004 {
		compatible = "qcom,gdsc";
		reg = <0x177004 0x4>;
		regulator-name = "ufs_phy_gdsc";
		};

		usb30_prim_gdsc: qcom,gdsc@10f004 {
		compatible = "qcom,gdsc";
		reg = <0x10f004 0x4>;
		regulator-name = "usb30_prim_gdsc";
		};

		usb30_sec_gdsc: qcom,gdsc@110004 {
		compatible = "qcom,gdsc";
		reg = <0x110004 0x4>;
		regulator-name = "usb30_sec_gdsc";
		};

		hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
		compatible = "qcom,gdsc";
		reg = <0x17d050 0x4>;
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		};

		hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
		compatible = "qcom,gdsc";
		reg = <0x17d058 0x4>;
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		};

		hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
		compatible = "qcom,gdsc";
		reg = <0x17d054 0x4>;
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		};

		hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c {
		compatible = "qcom,gdsc";
		reg = <0x17d06c 0x4>;
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		};

		/* CAM_CC GDSCs */
		bps_gdsc: qcom,gdsc@ad07004 {
		compatible = "qcom,gdsc";
		reg = <0xad07004 0x4>;
		regulator-name = "bps_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		qcom,support-hw-trigger;
		};

		ife_0_gdsc: qcom,gdsc@ad0a004 {
		compatible = "qcom,gdsc";
		reg = <0xad0a004 0x4>;
		regulator-name = "ife_0_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		};

		ife_1_gdsc: qcom,gdsc@ad0b004 {
		compatible = "qcom,gdsc";
		reg = <0xad0b004 0x4>;
		regulator-name = "ife_1_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		};

		ipe_0_gdsc: qcom,gdsc@ad08004 {
		compatible = "qcom,gdsc";
		reg = <0xad08004 0x4>;
		regulator-name = "ipe_0_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		qcom,support-hw-trigger;
		};

		sbi_gdsc: qcom,gdsc@ad09004 {
		compatible = "qcom,gdsc";
		reg = <0xad09004 0x4>;
		regulator-name = "sbi_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		};

		titan_top_gdsc: qcom,gdsc@ad0c144 {
		compatible = "qcom,gdsc";
		reg = <0xad0c144 0x4>;
		regulator-name = "titan_top_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		};

		/* DISP_CC GDSC */
		mdss_core_gdsc: qcom,gdsc@af03000 {
		compatible = "qcom,gdsc";
		reg = <0xaf03000 0x4>;
		regulator-name = "mdss_core_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		qcom,support-hw-trigger;
		};

		/* GPU_CC GDSCs */
		gpu_cx_hw_ctrl: syscon@3d91540 {
		compatible = "syscon";
		reg = <0x3d91540 0x4>;
		};

		gpu_cx_gdsc: qcom,gdsc@3d9106c {
		compatible = "qcom,gdsc";
		reg = <0x3d9106c 0x4>;
		regulator-name = "gpu_cx_gdsc";
		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
		parent-supply = <&VDD_CX_LEVEL>;
		qcom,no-status-check-on-disable;
		qcom,clk-dis-wait-val = <8>;
		qcom,gds-timeout = <500>;
		};

		gpu_gx_domain_addr: syscon@0x3d91508 {
		compatible = "syscon";
		reg = <0x3d91508 0x4>;
		};

		gpu_gx_sw_reset: syscon@0x3d91008 {
		compatible = "syscon";
		reg = <0x3d91008 0x4>;
		};

		gpu_gx_gdsc: qcom,gdsc@3d9100c {
		compatible = "qcom,gdsc";
		reg = <0x3d9100c 0x4>;
		regulator-name = "gpu_gx_gdsc";
		domain-addr = <&gpu_gx_domain_addr>;
		sw-reset = <&gpu_gx_sw_reset>;
		parent-supply = <&VDD_GFX_LEVEL>;
		vdd_parent-supply = <&VDD_GFX_LEVEL>;
		qcom,reset-aon-logic;
		};

		/* NPU GDSC */
		npu_core_gdsc: qcom,gdsc@9981004 {
		compatible = "qcom,gdsc";
		reg = <0x9981004 0x4>;
		regulator-name = "npu_core_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>;
		};

		/* VIDEO_CC GDSCs */
		mvs0_gdsc: qcom,gdsc@abf0d18 {
		compatible = "qcom,gdsc";
		reg = <0xabf0d18 0x4>;
		regulator-name = "mvs0_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		};

		mvs0c_gdsc: qcom,gdsc@abf0bf8 {
		compatible = "qcom,gdsc";
		reg = <0xabf0bf8 0x4>;
		regulator-name = "mvs0c_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		};

		mvs1_gdsc: qcom,gdsc@abf0d98 {
		compatible = "qcom,gdsc";
		reg = <0xabf0d98 0x4>;
		regulator-name = "mvs1_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		};

		mvs1c_gdsc: qcom,gdsc@abf0c98 {
		compatible = "qcom,gdsc";
		reg = <0xabf0c98 0x4>;
		regulator-name = "mvs1c_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		};

		ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xe00>; /* PHY regs */
		reg-names = "phy_mem";

arch/arm64/boot/dts/qcom/msm-arm-smmu-kona.dtsi

+10 −1

Original line number	Diff line number	Diff line
		@@ -19,6 +19,8 @@
		#size-cells = <1>;
		#address-cells = <1>;
		ranges;
		qcom,regulator-names = "vdd";
		vdd-supply = <&gpu_cx_gdsc>;
		interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
		@@ -180,6 +182,8 @@
		<0x15182210 0x8>;
		reg-names = "base", "status-reg";
		qcom,stream-id-range = <0x800 0x400>;
		qcom,regulator-names = "vdd";
		vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
		};

		mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 {
		@@ -188,7 +192,8 @@
		<0x15182218 0x8>;
		reg-names = "base", "status-reg";
		qcom,stream-id-range = <0xc00 0x400>;

		qcom,regulator-names = "vdd";
		vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
		};

		compute_dsp_1_tbu: compute_dsp_1_tbu@15195000 {
		@@ -229,6 +234,8 @@
		<0x15182240 0x8>;
		reg-names = "base", "status-reg";
		qcom,stream-id-range = <0x2000 0x400>;
		qcom,regulator-names = "vdd";
		vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>;
		};

		mnoc_sf_1_tbu: mnoc_sf_1_tbu@151a9000 {
		@@ -237,6 +244,8 @@
		<0x15182248 0x8>;
		reg-names = "base", "status-reg";
		qcom,stream-id-range = <0x2400 0x400>;
		qcom,regulator-names = "vdd";
		vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc>;
		};
		};