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Commit fa8198ea authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add support for cayman gart setup 



This patch sets up the gart in legacy mode.  We
probably want to switch to full VM mode at some point.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent fecf1d07

drivers/gpu/drm/radeon/ni.c

+92 −0
Original line number Diff line number Diff line
@@ -931,3 +931,95 @@ static void cayman_gpu_init(struct radeon_device *rdev) 
	udelay(50);

}



/*

 * GART

 */

void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)

{

	/* flush hdp cache */

	WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);



	/* bits 0-7 are the VM contexts0-7 */

	WREG32(VM_INVALIDATE_REQUEST, 1);

}



int cayman_pcie_gart_enable(struct radeon_device *rdev)

{

	int r;



	if (rdev->gart.table.vram.robj == NULL) {

		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");

		return -EINVAL;

	}

	r = radeon_gart_table_vram_pin(rdev);

	if (r)

		return r;

	radeon_gart_restore(rdev);

	/* Setup TLB control */

	WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB |

	       ENABLE_L1_FRAGMENT_PROCESSING |

	       SYSTEM_ACCESS_MODE_NOT_IN_SYS |

	       SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);

	/* Setup L2 cache */

	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |

	       ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |

	       ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |

	       EFFECTIVE_L2_QUEUE_SIZE(7) |

	       CONTEXT1_IDENTITY_ACCESS_MODE(1));

	WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);

	WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |

	       L2_CACHE_BIGK_FRAGMENT_SIZE(6));

	/* setup context0 */

	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

			(u32)(rdev->dummy_page.addr >> 12));

	WREG32(VM_CONTEXT0_CNTL2, 0);

	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);

	/* disable context1-7 */

	WREG32(VM_CONTEXT1_CNTL2, 0);

	WREG32(VM_CONTEXT1_CNTL, 0);



	cayman_pcie_gart_tlb_flush(rdev);

	rdev->gart.ready = true;

	return 0;

}



void cayman_pcie_gart_disable(struct radeon_device *rdev)

{

	int r;



	/* Disable all tables */

	WREG32(VM_CONTEXT0_CNTL, 0);

	WREG32(VM_CONTEXT1_CNTL, 0);

	/* Setup TLB control */

	WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |

	       SYSTEM_ACCESS_MODE_NOT_IN_SYS |

	       SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);

	/* Setup L2 cache */

	WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |

	       ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |

	       EFFECTIVE_L2_QUEUE_SIZE(7) |

	       CONTEXT1_IDENTITY_ACCESS_MODE(1));

	WREG32(VM_L2_CNTL2, 0);

	WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |

	       L2_CACHE_BIGK_FRAGMENT_SIZE(6));

	if (rdev->gart.table.vram.robj) {

		r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);

		if (likely(r == 0)) {

			radeon_bo_kunmap(rdev->gart.table.vram.robj);

			radeon_bo_unpin(rdev->gart.table.vram.robj);

			radeon_bo_unreserve(rdev->gart.table.vram.robj);

		}

	}

}



void cayman_pcie_gart_fini(struct radeon_device *rdev)

{

	cayman_pcie_gart_disable(rdev);

	radeon_gart_table_vram_free(rdev);

	radeon_gart_fini(rdev);

}

drivers/gpu/drm/radeon/nid.h

+57 −0
Original line number Diff line number Diff line
@@ -43,10 +43,66 @@ 


#define DMIF_ADDR_CONFIG  				0xBD4



#define VM_CONTEXT0_REQUEST_RESPONSE			0x1470

#define		REQUEST_TYPE(x)					(((x) & 0xf) << 0)

#define		RESPONSE_TYPE_MASK				0x000000F0

#define		RESPONSE_TYPE_SHIFT				4

#define VM_L2_CNTL					0x1400

#define		ENABLE_L2_CACHE					(1 << 0)

#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)

#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)

#define		ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE	(1 << 10)

#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 14)

#define		CONTEXT1_IDENTITY_ACCESS_MODE(x)		(((x) & 3) << 18)

/* CONTEXT1_IDENTITY_ACCESS_MODE

 * 0 physical = logical

 * 1 logical via context1 page table

 * 2 inside identity aperture use translation, outside physical = logical

 * 3 inside identity aperture physical = logical, outside use translation

 */

#define VM_L2_CNTL2					0x1404

#define		INVALIDATE_ALL_L1_TLBS				(1 << 0)

#define		INVALIDATE_L2_CACHE				(1 << 1)

#define VM_L2_CNTL3					0x1408

#define		BANK_SELECT(x)					((x) << 0)

#define		CACHE_UPDATE_MODE(x)				((x) << 6)

#define		L2_CACHE_BIGK_ASSOCIATIVITY			(1 << 20)

#define		L2_CACHE_BIGK_FRAGMENT_SIZE(x)			((x) << 15)

#define	VM_L2_STATUS					0x140C

#define		L2_BUSY						(1 << 0)

#define VM_CONTEXT0_CNTL				0x1410

#define		ENABLE_CONTEXT					(1 << 0)

#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)

#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)

#define VM_CONTEXT1_CNTL				0x1414

#define VM_CONTEXT0_CNTL2				0x1430

#define VM_CONTEXT1_CNTL2				0x1434

#define VM_INVALIDATE_REQUEST				0x1478

#define VM_INVALIDATE_RESPONSE				0x147c

#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x1518

#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR	0x151c

#define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x153C

#define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x155C

#define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x157C



#define MC_SHARED_CHMAP						0x2004

#define		NOOFCHAN_SHIFT					12

#define		NOOFCHAN_MASK					0x00003000

#define MC_SHARED_CHREMAP					0x2008



#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2034

#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2038

#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x203C

#define	MC_VM_MX_L1_TLB_CNTL				0x2064

#define		ENABLE_L1_TLB					(1 << 0)

#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)

#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)

#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)

#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)

#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)

#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)

#define		ENABLE_ADVANCED_DRIVER_MODEL			(1 << 6)



#define MC_SHARED_BLACKOUT_CNTL           		0x20ac

#define	MC_ARB_RAMCFG					0x2760

#define		NOOFBANK_SHIFT					0
@@ -87,6 +143,7 @@ 


#define	CONFIG_MEMSIZE					0x5428



#define HDP_MEM_COHERENCY_FLUSH_CNTL			0x5480

#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0



#define	GRBM_CNTL					0x8000