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Commit fa6f071d authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: move gen8 irq shifts to intel_lrc.c 



The only usage outside the intel_lrc.c file is in the ringbuffer
init, but the irq mask calculated there is then overwritten for
all engines that have a non-zero shift, so we can drop it.

This change is not aimed at code saving but at removing from
intel_engines information that does not apply to all gens that have
the engine. When checking without the temporary WARN_ON, code size
is basically unchanged.

v2: make the irq_shifts array static const
v3: rebase, move irq_shifts array to logical_ring_default_irqs
v4: move array inside the if and use u8 for it (Chris)

Suggested-by: default avatarMichel Thierry <michel.thierry@intel.com>
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180314182653.26981-4-daniele.ceraolospurio@intel.com
parent 210060ed

drivers/gpu/drm/i915/intel_engine_cs.c

+0 −10
Original line number Original line Diff line number Diff line
@@ -92,7 +92,6 @@ struct engine_info { 
		u32 gen : 8;

		u32 gen : 8;

		u32 base : 24;

		u32 base : 24;

	} mmio_bases[MAX_MMIO_BASES];

	} mmio_bases[MAX_MMIO_BASES];

	unsigned irq_shift;

};

};





static const struct engine_info intel_engines[] = {

static const struct engine_info intel_engines[] = {
@@ -104,7 +103,6 @@ static const struct engine_info intel_engines[] = { 
		.mmio_bases = {

		.mmio_bases = {

			{ .gen = 1, .base = RENDER_RING_BASE }

			{ .gen = 1, .base = RENDER_RING_BASE }

		},

		},

		.irq_shift = GEN8_RCS_IRQ_SHIFT,

	},

	},

	[BCS] = {

	[BCS] = {

		.hw_id = BCS_HW,

		.hw_id = BCS_HW,
@@ -114,7 +112,6 @@ static const struct engine_info intel_engines[] = { 
		.mmio_bases = {

		.mmio_bases = {

			{ .gen = 6, .base = BLT_RING_BASE }

			{ .gen = 6, .base = BLT_RING_BASE }

		},

		},

		.irq_shift = GEN8_BCS_IRQ_SHIFT,

	},

	},

	[VCS] = {

	[VCS] = {

		.hw_id = VCS_HW,

		.hw_id = VCS_HW,
@@ -126,7 +123,6 @@ static const struct engine_info intel_engines[] = { 
			{ .gen = 6, .base = GEN6_BSD_RING_BASE },

			{ .gen = 6, .base = GEN6_BSD_RING_BASE },

			{ .gen = 4, .base = BSD_RING_BASE }

			{ .gen = 4, .base = BSD_RING_BASE }

		},

		},

		.irq_shift = GEN8_VCS1_IRQ_SHIFT,

	},

	},

	[VCS2] = {

	[VCS2] = {

		.hw_id = VCS2_HW,

		.hw_id = VCS2_HW,
@@ -137,7 +133,6 @@ static const struct engine_info intel_engines[] = { 
			{ .gen = 11, .base = GEN11_BSD2_RING_BASE },

			{ .gen = 11, .base = GEN11_BSD2_RING_BASE },

			{ .gen = 8, .base = GEN8_BSD2_RING_BASE }

			{ .gen = 8, .base = GEN8_BSD2_RING_BASE }

		},

		},

		.irq_shift = GEN8_VCS2_IRQ_SHIFT,

	},

	},

	[VCS3] = {

	[VCS3] = {

		.hw_id = VCS3_HW,

		.hw_id = VCS3_HW,
@@ -147,7 +142,6 @@ static const struct engine_info intel_engines[] = { 
		.mmio_bases = {

		.mmio_bases = {

			{ .gen = 11, .base = GEN11_BSD3_RING_BASE }

			{ .gen = 11, .base = GEN11_BSD3_RING_BASE }

		},

		},

		.irq_shift = 0, /* not used */

	},

	},

	[VCS4] = {

	[VCS4] = {

		.hw_id = VCS4_HW,

		.hw_id = VCS4_HW,
@@ -157,7 +151,6 @@ static const struct engine_info intel_engines[] = { 
		.mmio_bases = {

		.mmio_bases = {

			{ .gen = 11, .base = GEN11_BSD4_RING_BASE }

			{ .gen = 11, .base = GEN11_BSD4_RING_BASE }

		},

		},

		.irq_shift = 0, /* not used */

	},

	},

	[VECS] = {

	[VECS] = {

		.hw_id = VECS_HW,

		.hw_id = VECS_HW,
@@ -168,7 +161,6 @@ static const struct engine_info intel_engines[] = { 
			{ .gen = 11, .base = GEN11_VEBOX_RING_BASE },

			{ .gen = 11, .base = GEN11_VEBOX_RING_BASE },

			{ .gen = 7, .base = VEBOX_RING_BASE }

			{ .gen = 7, .base = VEBOX_RING_BASE }

		},

		},

		.irq_shift = GEN8_VECS_IRQ_SHIFT,

	},

	},

	[VECS2] = {

	[VECS2] = {

		.hw_id = VECS2_HW,

		.hw_id = VECS2_HW,
@@ -178,7 +170,6 @@ static const struct engine_info intel_engines[] = { 
		.mmio_bases = {

		.mmio_bases = {

			{ .gen = 11, .base = GEN11_VEBOX2_RING_BASE }

			{ .gen = 11, .base = GEN11_VEBOX2_RING_BASE }

		},

		},

		.irq_shift = 0, /* not used */

	},

	},

};

};
@@ -301,7 +292,6 @@ intel_engine_setup(struct drm_i915_private *dev_priv, 
	__sprint_engine_name(engine->name, info);

	__sprint_engine_name(engine->name, info);

	engine->hw_id = engine->guc_id = info->hw_id;

	engine->hw_id = engine->guc_id = info->hw_id;

	engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases);

	engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases);

	engine->irq_shift = info->irq_shift;

	engine->class = info->class;

	engine->class = info->class;

	engine->instance = info->instance;

	engine->instance = info->instance;

drivers/gpu/drm/i915/intel_lrc.c

+14 −1
Original line number Original line Diff line number Diff line
@@ -2118,7 +2118,20 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) 
static inline void

static inline void

logical_ring_default_irqs(struct intel_engine_cs *engine)

logical_ring_default_irqs(struct intel_engine_cs *engine)

{

{

	unsigned shift = engine->irq_shift;

	unsigned int shift = 0;



	if (INTEL_GEN(engine->i915) < 11) {

		const u8 irq_shifts[] = {

			[RCS]  = GEN8_RCS_IRQ_SHIFT,

			[BCS]  = GEN8_BCS_IRQ_SHIFT,

			[VCS]  = GEN8_VCS1_IRQ_SHIFT,

			[VCS2] = GEN8_VCS2_IRQ_SHIFT,

			[VECS] = GEN8_VECS_IRQ_SHIFT,

		};



		shift = irq_shifts[engine->id];

	}



	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;

	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;

	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;

	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;

}

}

drivers/gpu/drm/i915/intel_ringbuffer.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -1944,8 +1944,6 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, 
static void intel_ring_init_irq(struct drm_i915_private *dev_priv,

static void intel_ring_init_irq(struct drm_i915_private *dev_priv,

				struct intel_engine_cs *engine)

				struct intel_engine_cs *engine)

{

{

	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;



	if (INTEL_GEN(dev_priv) >= 6) {

	if (INTEL_GEN(dev_priv) >= 6) {

		engine->irq_enable = gen6_irq_enable;

		engine->irq_enable = gen6_irq_enable;

		engine->irq_disable = gen6_irq_disable;

		engine->irq_disable = gen6_irq_disable;
@@ -2030,6 +2028,8 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) 
	if (HAS_L3_DPF(dev_priv))

	if (HAS_L3_DPF(dev_priv))

		engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;

		engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;





	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;



	if (INTEL_GEN(dev_priv) >= 6) {

	if (INTEL_GEN(dev_priv) >= 6) {

		engine->init_context = intel_rcs_ctx_init;

		engine->init_context = intel_rcs_ctx_init;

		engine->emit_flush = gen7_render_ring_flush;

		engine->emit_flush = gen7_render_ring_flush;

drivers/gpu/drm/i915/intel_ringbuffer.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -331,7 +331,6 @@ struct intel_engine_cs { 
	u8 instance;

	u8 instance;

	u32 context_size;

	u32 context_size;

	u32 mmio_base;

	u32 mmio_base;

	unsigned int irq_shift;





	struct intel_ring *buffer;

	struct intel_ring *buffer;

	struct intel_timeline *timeline;

	struct intel_timeline *timeline;