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Unverified Commit fa4127c5 authored by Giulio Benetti's avatar Giulio Benetti Committed by Maxime Ripard
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drm/sun4i: fix HSYNC and VSYNC polarity 



Differently from other Lcd signals, HSYNC and VSYNC signals
result inverted if their bits are cleared to 0.

Invert their settings of IO_POL register.

Signed-off-by: default avatarGiulio Benetti <giulio.benetti@micronovasrl.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1518717288-123578-1-git-send-email-giulio.benetti@micronovasrl.com
parent cd0e93d8

drivers/gpu/drm/sun4i/sun4i_tcon.c

+2 −2
Original line number Diff line number Diff line
@@ -394,10 +394,10 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, 
		     SUN4I_TCON0_BASIC3_H_SYNC(hsync));



	/* Setup the polarity of the various signals */

	if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))

	if (mode->flags & DRM_MODE_FLAG_PHSYNC)

		val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;



	if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))

	if (mode->flags & DRM_MODE_FLAG_PVSYNC)

		val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;



	regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,