Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f989086c authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard
Browse files

ARM: dts: sunxi: add dtsi file for V3s SoC 



As we have the pinctrl and clock support for the V3s SoC, it's now to
run a mainline Linux on it.

So add a .dtsi file for it.

Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.xyz>
[Maxime: Removed the dependency on the CCU headers]
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent c9c9ac71

arch/arm/boot/dts/sun8i-v3s.dtsi

0 → 100644
+309 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>

 *

 * This file is dual-licensed: you can use it either under the terms

 * of the GPL or the X11 license, at your option. Note that this dual

 * licensing only applies to this file, and not this project as a

 * whole.

 *

 *  a) This file is free software; you can redistribute it and/or

 *     modify it under the terms of the GNU General Public License as

 *     published by the Free Software Foundation; either version 2 of the

 *     License, or (at your option) any later version.

 *

 *     This file is distributed in the hope that it will be useful,

 *     but WITHOUT ANY WARRANTY; without even the implied warranty of

 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *     GNU General Public License for more details.

 *

 * Or, alternatively,

 *

 *  b) Permission is hereby granted, free of charge, to any person

 *     obtaining a copy of this software and associated documentation

 *     files (the "Software"), to deal in the Software without

 *     restriction, including without limitation the rights to use,

 *     copy, modify, merge, publish, distribute, sublicense, and/or

 *     sell copies of the Software, and to permit persons to whom the

 *     Software is furnished to do so, subject to the following

 *     conditions:

 *

 *     The above copyright notice and this permission notice shall be

 *     included in all copies or substantial portions of the Software.

 *

 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES

 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 *     OTHER DEALINGS IN THE SOFTWARE.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	#address-cells = <1>;

	#size-cells = <1>;

	interrupt-parent = <&gic>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <0>;

			clocks = <&ccu 14>;

		};

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		osc24M: osc24M_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <24000000>;

			clock-output-names = "osc24M";

		};



		osc32k: osc32k_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <32768>;

			clock-output-names = "osc32k";

		};

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		mmc0: mmc@01c0f000 {

			compatible = "allwinner,sun7i-a20-mmc";

			reg = <0x01c0f000 0x1000>;

			clocks = <&ccu 22>,

				 <&ccu 45>,

				 <&ccu 47>,

				 <&ccu 46>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			resets = <&ccu 7>;

			reset-names = "ahb";

			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		mmc1: mmc@01c10000 {

			compatible = "allwinner,sun7i-a20-mmc";

			reg = <0x01c10000 0x1000>;

			clocks = <&ccu 23>,

				 <&ccu 48>,

				 <&ccu 50>,

				 <&ccu 49>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			resets = <&ccu 8>;

			reset-names = "ahb";

			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		mmc2: mmc@01c11000 {

			compatible = "allwinner,sun7i-a20-mmc";

			reg = <0x01c11000 0x1000>;

			clocks = <&ccu 24>,

				 <&ccu 51>,

				 <&ccu 53>,

				 <&ccu 52>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			resets = <&ccu 9>;

			reset-names = "ahb";

			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		usb_otg: usb@01c19000 {

			compatible = "allwinner,sun8i-h3-musb";

			reg = <0x01c19000 0x0400>;

			clocks = <&ccu 29>;

			resets = <&ccu 17>;

			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "mc";

			phys = <&usbphy 0>;

			phy-names = "usb";

			extcon = <&usbphy 0>;

			status = "disabled";

		};



		usbphy: phy@01c19400 {

			compatible = "allwinner,sun8i-v3s-usb-phy";

			reg = <0x01c19400 0x2c>,

			      <0x01c1a800 0x4>;

			reg-names = "phy_ctrl",

				    "pmu0";

			clocks = <&ccu 56>;

			clock-names = "usb0_phy";

			resets = <&ccu 0>;

			reset-names = "usb0_reset";

			status = "disabled";

			#phy-cells = <1>;

		};



		ccu: clock@01c20000 {

			compatible = "allwinner,sun8i-v3s-ccu";

			reg = <0x01c20000 0x400>;

			clocks = <&osc24M>, <&osc32k>;

			clock-names = "hosc", "losc";

			#clock-cells = <1>;

			#reset-cells = <1>;

		};



		rtc: rtc@01c20400 {

			compatible = "allwinner,sun6i-a31-rtc";

			reg = <0x01c20400 0x54>;

			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;

		};



		pio: pinctrl@01c20800 {

			compatible = "allwinner,sun8i-v3s-pinctrl";

			reg = <0x01c20800 0x400>;

			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu 37>, <&osc24M>, <&osc32k>;

			clock-names = "apb", "hosc", "losc";

			gpio-controller;

			#gpio-cells = <3>;

			interrupt-controller;

			#interrupt-cells = <3>;



			i2c0_pins: i2c0 {

				pins = "PB6", "PB7";

				function = "i2c0";

			};



			uart0_pins_a: uart0@0 {

				pins = "PB8", "PB9";

				function = "uart0";

			};



			mmc0_pins_a: mmc0@0 {

				pins = "PF0", "PF1", "PF2", "PF3",

				       "PF4", "PF5";

				function = "mmc0";

				drive-strength = <30>;

				bias-pull-up;

			};

		};



		timer@01c20c00 {

			compatible = "allwinner,sun4i-a10-timer";

			reg = <0x01c20c00 0xa0>;

			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&osc24M>;

		};



		wdt0: watchdog@01c20ca0 {

			compatible = "allwinner,sun6i-a31-wdt";

			reg = <0x01c20ca0 0x20>;

			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

		};



		uart0: serial@01c28000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28000 0x400>;

			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu 40>;

			resets = <&ccu 49>;

			status = "disabled";

		};



		uart1: serial@01c28400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28400 0x400>;

			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu 41>;

			resets = <&ccu 50>;

			status = "disabled";

		};



		uart2: serial@01c28800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28800 0x400>;

			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu 42>;

			resets = <&ccu 51>;

			status = "disabled";

		};



		i2c0: i2c@01c2ac00 {

			compatible = "allwinner,sun6i-a31-i2c";

			reg = <0x01c2ac00 0x400>;

			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu 38>;

			resets = <&ccu 46>;

			pinctrl-names = "default";

			pinctrl-0 = <&i2c0_pins>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		i2c1: i2c@01c2b000 {

			compatible = "allwinner,sun6i-a31-i2c";

			reg = <0x01c2b000 0x400>;

			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu 39>;

			resets = <&ccu 47>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		gic: interrupt-controller@01c81000 {

			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";

			reg = <0x01c81000 0x1000>,

			      <0x01c82000 0x1000>,

			      <0x01c84000 0x2000>,

			      <0x01c86000 0x2000>;

			interrupt-controller;

			#interrupt-cells = <3>;

			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		};

	};

};