Loading drivers/gpu/msm/adreno-gpulist.h +10 −0 Original line number Diff line number Diff line Loading @@ -331,6 +331,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_minor = 0x003, .gpmu_tsens = 0x000C000D, .max_power = 5448, .prim_fifo_threshold = 0x0018000, }, { .gpurev = ADRENO_REV_A630, Loading @@ -352,6 +353,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_minor = 0x003, .gpmu_tsens = 0x000C000D, .max_power = 5448, .prim_fifo_threshold = 0x0018000, }, { .gpurev = ADRENO_REV_A615, Loading @@ -371,6 +373,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmufw_name = "a630_gmu.bin", .gpmu_major = 0x1, .gpmu_minor = 0x003, .prim_fifo_threshold = 0x0018000, }, { .gpurev = ADRENO_REV_A618, Loading @@ -390,6 +393,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmufw_name = "a630_gmu.bin", .gpmu_major = 0x1, .gpmu_minor = 0x007, .prim_fifo_threshold = 0x0018000, }, { .gpurev = ADRENO_REV_A640, Loading @@ -412,6 +416,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_tsens = 0x000C000D, .max_power = 5448, .va_padding = SZ_64K, .prim_fifo_threshold = 0x00200000, }, { .gpurev = ADRENO_REV_A640, Loading @@ -433,6 +438,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_minor = 0x000, .gpmu_tsens = 0x000C000D, .max_power = 5448, .prim_fifo_threshold = 0x00200000, }, { .gpurev = ADRENO_REV_A650, Loading @@ -452,6 +458,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_minor = 0x000, .gpmu_tsens = 0x000C000D, .max_power = 5448, .prim_fifo_threshold = 0x00300000, }, { .gpurev = ADRENO_REV_A680, Loading @@ -471,6 +478,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_minor = 0x000, .gpmu_tsens = 0x000C000D, .max_power = 5448, .prim_fifo_threshold = 0x00400000, }, { .gpurev = ADRENO_REV_A612, Loading @@ -488,6 +496,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .num_protected_regs = 0x20, .busy_mask = 0xFFFFFFFE, .gpmufw_name = "a612_rgmu.bin", .prim_fifo_threshold = 0x00080000, }, { .gpurev = ADRENO_REV_A616, Loading @@ -507,5 +516,6 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmufw_name = "a630_gmu.bin", .gpmu_major = 0x1, .gpmu_minor = 0x003, .prim_fifo_threshold = 0x0018000, }, }; drivers/gpu/msm/adreno.h +1 −0 Original line number Diff line number Diff line Loading @@ -418,6 +418,7 @@ struct adreno_gpu_core { unsigned int gpmu_tsens; unsigned int max_power; uint64_t va_padding; unsigned int prim_fifo_threshold; }; Loading drivers/gpu/msm/adreno_a6xx.c +31 −20 Original line number Diff line number Diff line Loading @@ -23,6 +23,8 @@ #include "kgsl_trace.h" #define MIN_HBB 13 #define HBB_LOWER_MASK 0x3 #define HBB_UPPER_SHIFT 0x2 static const struct adreno_vbif_data a630_vbif[] = { {A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009}, Loading Loading @@ -832,8 +834,10 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) static void a6xx_start(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); unsigned int bit, mal, mode, glbl_inv; unsigned int bit, lower_bit, mal, mode, glbl_inv, upper_bit; unsigned int uavflagprd_inv; unsigned int amsbc = 0; unsigned int rgb565_predicator = 0; static bool patch_reglist; /* runtime adjust callbacks based on feature sets */ Loading Loading @@ -899,14 +903,8 @@ static void a6xx_start(struct adreno_device *adreno_dev) } /* Setting the primFifo thresholds values */ if (adreno_is_a640(adreno_dev)) kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x400 << 11)); else if (adreno_is_a680(adreno_dev)) kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x800 << 11)); else if (adreno_is_a612(adreno_dev)) kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x100 << 11)); else kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, adreno_dev->gpucore->prim_fifo_threshold); /* Set the AHB default slave response to "ERROR" */ kgsl_regwrite(device, A6XX_CP_AHB_CNTL, 0x1); Loading Loading @@ -944,29 +942,42 @@ static void a6xx_start(struct adreno_device *adreno_dev) mode = 0; amsbc = 1; /* Only valid for A640 and A680 */ break; case KGSL_UBWC_4_0: rgb565_predicator = 1; amsbc = 1; break; default: break; } if (bit >= 13 && bit <= 16) bit = (bit - 13) & 0x03; else bit = 0; if (bit >= 13 && bit <= 17) { bit = bit - MIN_HBB; lower_bit = bit & HBB_LOWER_MASK; upper_bit = (bit >> HBB_UPPER_SHIFT) & 1; } else { lower_bit = 0; upper_bit = 0; } mal = (mal == 64) ? 1 : 0; /* (1 << 29)globalInvFlushFilterDis bit needs to be set for A630 V1 */ glbl_inv = (adreno_is_a630v1(adreno_dev)) ? 1 : 0; uavflagprd_inv = (adreno_is_a650(adreno_dev)) ? 2 : 0; kgsl_regwrite(device, A6XX_RB_NC_MODE_CNTL, (rgb565_predicator << 11)| (upper_bit << 10) | (amsbc << 4) | (mal << 3) | (lower_bit << 1) | mode); kgsl_regwrite(device, A6XX_TPL1_NC_MODE_CNTL, (upper_bit << 4) | (mal << 3) | (lower_bit << 1) | mode); kgsl_regwrite(device, A6XX_RB_NC_MODE_CNTL, (amsbc << 4) | (mal << 3) | (bit << 1) | mode); kgsl_regwrite(device, A6XX_TPL1_NC_MODE_CNTL, (mal << 3) | (bit << 1) | mode); kgsl_regwrite(device, A6XX_SP_NC_MODE_CNTL, (mal << 3) | (bit << 1) | mode); kgsl_regwrite(device, A6XX_SP_NC_MODE_CNTL, (upper_bit << 10) | (mal << 3) | (uavflagprd_inv << 4) | (lower_bit << 1) | mode); kgsl_regwrite(device, A6XX_UCHE_MODE_CNTL, (glbl_inv << 29) | (mal << 23) | (bit << 21)); (mal << 23) | (lower_bit << 21)); /* Set hang detection threshold to 0x3FFFFF * 16 cycles */ kgsl_regwrite(device, A6XX_RBBM_INTERFACE_HANG_INT_CNTL, Loading include/uapi/linux/msm_kgsl.h +1 −0 Original line number Diff line number Diff line Loading @@ -236,6 +236,7 @@ enum kgsl_user_mem_type { #define KGSL_UBWC_1_0 1 #define KGSL_UBWC_2_0 2 #define KGSL_UBWC_3_0 3 #define KGSL_UBWC_4_0 4 /* * Reset status values for context Loading Loading
drivers/gpu/msm/adreno-gpulist.h +10 −0 Original line number Diff line number Diff line Loading @@ -331,6 +331,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_minor = 0x003, .gpmu_tsens = 0x000C000D, .max_power = 5448, .prim_fifo_threshold = 0x0018000, }, { .gpurev = ADRENO_REV_A630, Loading @@ -352,6 +353,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_minor = 0x003, .gpmu_tsens = 0x000C000D, .max_power = 5448, .prim_fifo_threshold = 0x0018000, }, { .gpurev = ADRENO_REV_A615, Loading @@ -371,6 +373,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmufw_name = "a630_gmu.bin", .gpmu_major = 0x1, .gpmu_minor = 0x003, .prim_fifo_threshold = 0x0018000, }, { .gpurev = ADRENO_REV_A618, Loading @@ -390,6 +393,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmufw_name = "a630_gmu.bin", .gpmu_major = 0x1, .gpmu_minor = 0x007, .prim_fifo_threshold = 0x0018000, }, { .gpurev = ADRENO_REV_A640, Loading @@ -412,6 +416,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_tsens = 0x000C000D, .max_power = 5448, .va_padding = SZ_64K, .prim_fifo_threshold = 0x00200000, }, { .gpurev = ADRENO_REV_A640, Loading @@ -433,6 +438,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_minor = 0x000, .gpmu_tsens = 0x000C000D, .max_power = 5448, .prim_fifo_threshold = 0x00200000, }, { .gpurev = ADRENO_REV_A650, Loading @@ -452,6 +458,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_minor = 0x000, .gpmu_tsens = 0x000C000D, .max_power = 5448, .prim_fifo_threshold = 0x00300000, }, { .gpurev = ADRENO_REV_A680, Loading @@ -471,6 +478,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_minor = 0x000, .gpmu_tsens = 0x000C000D, .max_power = 5448, .prim_fifo_threshold = 0x00400000, }, { .gpurev = ADRENO_REV_A612, Loading @@ -488,6 +496,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .num_protected_regs = 0x20, .busy_mask = 0xFFFFFFFE, .gpmufw_name = "a612_rgmu.bin", .prim_fifo_threshold = 0x00080000, }, { .gpurev = ADRENO_REV_A616, Loading @@ -507,5 +516,6 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmufw_name = "a630_gmu.bin", .gpmu_major = 0x1, .gpmu_minor = 0x003, .prim_fifo_threshold = 0x0018000, }, };
drivers/gpu/msm/adreno.h +1 −0 Original line number Diff line number Diff line Loading @@ -418,6 +418,7 @@ struct adreno_gpu_core { unsigned int gpmu_tsens; unsigned int max_power; uint64_t va_padding; unsigned int prim_fifo_threshold; }; Loading
drivers/gpu/msm/adreno_a6xx.c +31 −20 Original line number Diff line number Diff line Loading @@ -23,6 +23,8 @@ #include "kgsl_trace.h" #define MIN_HBB 13 #define HBB_LOWER_MASK 0x3 #define HBB_UPPER_SHIFT 0x2 static const struct adreno_vbif_data a630_vbif[] = { {A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009}, Loading Loading @@ -832,8 +834,10 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) static void a6xx_start(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); unsigned int bit, mal, mode, glbl_inv; unsigned int bit, lower_bit, mal, mode, glbl_inv, upper_bit; unsigned int uavflagprd_inv; unsigned int amsbc = 0; unsigned int rgb565_predicator = 0; static bool patch_reglist; /* runtime adjust callbacks based on feature sets */ Loading Loading @@ -899,14 +903,8 @@ static void a6xx_start(struct adreno_device *adreno_dev) } /* Setting the primFifo thresholds values */ if (adreno_is_a640(adreno_dev)) kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x400 << 11)); else if (adreno_is_a680(adreno_dev)) kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x800 << 11)); else if (adreno_is_a612(adreno_dev)) kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x100 << 11)); else kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, adreno_dev->gpucore->prim_fifo_threshold); /* Set the AHB default slave response to "ERROR" */ kgsl_regwrite(device, A6XX_CP_AHB_CNTL, 0x1); Loading Loading @@ -944,29 +942,42 @@ static void a6xx_start(struct adreno_device *adreno_dev) mode = 0; amsbc = 1; /* Only valid for A640 and A680 */ break; case KGSL_UBWC_4_0: rgb565_predicator = 1; amsbc = 1; break; default: break; } if (bit >= 13 && bit <= 16) bit = (bit - 13) & 0x03; else bit = 0; if (bit >= 13 && bit <= 17) { bit = bit - MIN_HBB; lower_bit = bit & HBB_LOWER_MASK; upper_bit = (bit >> HBB_UPPER_SHIFT) & 1; } else { lower_bit = 0; upper_bit = 0; } mal = (mal == 64) ? 1 : 0; /* (1 << 29)globalInvFlushFilterDis bit needs to be set for A630 V1 */ glbl_inv = (adreno_is_a630v1(adreno_dev)) ? 1 : 0; uavflagprd_inv = (adreno_is_a650(adreno_dev)) ? 2 : 0; kgsl_regwrite(device, A6XX_RB_NC_MODE_CNTL, (rgb565_predicator << 11)| (upper_bit << 10) | (amsbc << 4) | (mal << 3) | (lower_bit << 1) | mode); kgsl_regwrite(device, A6XX_TPL1_NC_MODE_CNTL, (upper_bit << 4) | (mal << 3) | (lower_bit << 1) | mode); kgsl_regwrite(device, A6XX_RB_NC_MODE_CNTL, (amsbc << 4) | (mal << 3) | (bit << 1) | mode); kgsl_regwrite(device, A6XX_TPL1_NC_MODE_CNTL, (mal << 3) | (bit << 1) | mode); kgsl_regwrite(device, A6XX_SP_NC_MODE_CNTL, (mal << 3) | (bit << 1) | mode); kgsl_regwrite(device, A6XX_SP_NC_MODE_CNTL, (upper_bit << 10) | (mal << 3) | (uavflagprd_inv << 4) | (lower_bit << 1) | mode); kgsl_regwrite(device, A6XX_UCHE_MODE_CNTL, (glbl_inv << 29) | (mal << 23) | (bit << 21)); (mal << 23) | (lower_bit << 21)); /* Set hang detection threshold to 0x3FFFFF * 16 cycles */ kgsl_regwrite(device, A6XX_RBBM_INTERFACE_HANG_INT_CNTL, Loading
include/uapi/linux/msm_kgsl.h +1 −0 Original line number Diff line number Diff line Loading @@ -236,6 +236,7 @@ enum kgsl_user_mem_type { #define KGSL_UBWC_1_0 1 #define KGSL_UBWC_2_0 2 #define KGSL_UBWC_3_0 3 #define KGSL_UBWC_4_0 4 /* * Reset status values for context Loading