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Commit f8fc94db authored by Michel Pollet's avatar Michel Pollet Committed by Simon Horman
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ARM: dts: Renesas R9A06G032 SMP enable method 



Add a special enable method for the second CA7 of the R9A06G032
as well as the default value for the "cpu-release-addr" property.

Signed-off-by: default avatarMichel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent df7112c9

arch/arm/boot/dts/r9a06g032.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 
			compatible = "arm,cortex-a7";

			reg = <1>;

			clocks = <&sysctrl 84>;

			enable-method = "renesas,r9a06g032-smp";

			cpu-release-addr = <0 0x4000c204>;

		};

	};