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Commit f8f06f52 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: update initial lines calculation"

parents cde1d6cd adb6a235

drivers/gpu/drm/msm/sde/sde_encoder.c

+21 −18
Original line number Original line Diff line number Diff line
@@ -1160,25 +1160,28 @@ static void _sde_encoder_dsc_pclk_param_calc(struct msm_display_dsc_info *dsc, 
static int _sde_encoder_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,

static int _sde_encoder_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,

		int enc_ip_width)

		int enc_ip_width)

{

{

	int ssm_delay, total_pixels, soft_slice_per_enc;

	int max_ssm_delay, max_se_size, obuf_latency;

	int input_ssm_out_latency, base_hs_latency;

	int multi_hs_extra_latency,  mux_word_size;



	/* Hardent core config */

	int max_muxword_size = 48;

	int output_rate = 64;

	int rtl_max_bpc = 10;

	int pipeline_latency = 28;



	max_se_size = 4 * (rtl_max_bpc + 1);

	max_ssm_delay = max_se_size + max_muxword_size - 1;

	mux_word_size = (dsc->bpc >= 12 ? 64 : 48);

	input_ssm_out_latency = pipeline_latency + (3 * (max_ssm_delay + 2));

	obuf_latency = DIV_ROUND_UP((9 * output_rate +

				mux_word_size), dsc->bpp) + 1;

	base_hs_latency = dsc->initial_xmit_delay + input_ssm_out_latency

				+ obuf_latency;

	multi_hs_extra_latency = DIV_ROUND_UP((8 * dsc->chunk_size), dsc->bpp);

	dsc->initial_lines = DIV_ROUND_UP((base_hs_latency +

				multi_hs_extra_latency), dsc->slice_width);





	soft_slice_per_enc = enc_ip_width / dsc->slice_width;



	/*

	 * minimum number of initial line pixels is a sum of:

	 * 1. sub-stream multiplexer delay (83 groups for 8bpc,

	 *    91 for 10 bpc) * 3

	 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3

	 * 3. the initial xmit delay

	 * 4. total pipeline delay through the "lock step" of encoder (47)

	 * 5. 6 additional pixels as the output of the rate buffer is

	 *    48 bits wide

	 */

	ssm_delay = ((dsc->bpc < 10) ? 84 : 92);

	total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;

	if (soft_slice_per_enc > 1)

		total_pixels += (ssm_delay * 3);

	dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->slice_width);

	return 0;

	return 0;

}

}

drivers/gpu/drm/msm/sde/sde_hw_dsc.c

+1 −5
Original line number Original line Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

// SPDX-License-Identifier: GPL-2.0-only

/*

/*

 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 */

 */





#include "sde_hw_mdss.h"

#include "sde_hw_mdss.h"
@@ -49,7 +49,6 @@ static void sde_hw_dsc_config(struct sde_hw_dsc *hw_dsc, 
	u32 data;

	u32 data;

	int bpp, lsb;

	int bpp, lsb;

	u32 initial_lines = dsc->initial_lines;

	u32 initial_lines = dsc->initial_lines;

	bool is_cmd_mode = !(mode & BIT(2));

	struct sde_hw_blk_reg_map *dsc_c = &hw_dsc->hw;

	struct sde_hw_blk_reg_map *dsc_c = &hw_dsc->hw;





	SDE_REG_WRITE(dsc_c, DSC_COMMON_MODE, mode);

	SDE_REG_WRITE(dsc_c, DSC_COMMON_MODE, mode);
@@ -58,9 +57,6 @@ static void sde_hw_dsc_config(struct sde_hw_dsc *hw_dsc, 
	if (ich_reset_override)

	if (ich_reset_override)

		data = 3 << 28;

		data = 3 << 28;





	if (is_cmd_mode)

		initial_lines += 1;



	data |= (initial_lines << 20);

	data |= (initial_lines << 20);

	data |= (dsc->slice_last_group_size << 18);

	data |= (dsc->slice_last_group_size << 18);

	/* bpp is 6.4 format, 4 LSBs bits are for fractional part */

	/* bpp is 6.4 format, 4 LSBs bits are for fractional part */