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Commit f8973cf4 authored by Manikanta Maddireddy's avatar Manikanta Maddireddy Committed by Thierry Reding
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arm64: tegra: Add PCIe node for Tegra186 



Tegra186 has three PCIe controllers, which can be operated
in 401, 211 or 111 lane combinations. Add DT support for
PCIe controllers.

Signed-off-by: default avatarManikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Tested-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent effc4b44

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+80 −0
Original line number Diff line number Diff line
@@ -355,6 +355,86 @@ 
		nvidia,bpmp = <&bpmp>;

	};



	pcie@10003000 {

		compatible = "nvidia,tegra186-pcie";

		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;

		device_type = "pci";

		reg = <0x0 0x10003000 0x0 0x00000800   /* PADS registers */

		       0x0 0x10003800 0x0 0x00000800   /* AFI registers */

		       0x0 0x40000000 0x0 0x10000000>; /* configuration space */

		reg-names = "pads", "afi", "cs";



		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */

		interrupt-names = "intr", "msi";



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;



		bus-range = <0x00 0xff>;

		#address-cells = <3>;

		#size-cells = <2>;



		ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000   /* port 0 configuration space */

			  0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */

			  0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */

			  0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */

			  0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */

			  0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */



		clocks = <&bpmp TEGRA186_CLK_AFI>,

			 <&bpmp TEGRA186_CLK_PCIE>,

			 <&bpmp TEGRA186_CLK_PLLE>;

		clock-names = "afi", "pex", "pll_e";



		resets = <&bpmp TEGRA186_RESET_AFI>,

			 <&bpmp TEGRA186_RESET_PCIE>,

			 <&bpmp TEGRA186_RESET_PCIEXCLK>;

		reset-names = "afi", "pex", "pcie_x";



		status = "disabled";



		pci@1,0 {

			device_type = "pci";

			assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;

			reg = <0x000800 0 0 0 0>;

			status = "disabled";



			#address-cells = <3>;

			#size-cells = <2>;

			ranges;



			nvidia,num-lanes = <2>;

		};



		pci@2,0 {

			device_type = "pci";

			assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;

			reg = <0x001000 0 0 0 0>;

			status = "disabled";



			#address-cells = <3>;

			#size-cells = <2>;

			ranges;



			nvidia,num-lanes = <1>;

		};



		pci@3,0 {

			device_type = "pci";

			assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;

			reg = <0x001800 0 0 0 0>;

			status = "disabled";



			#address-cells = <3>;

			#size-cells = <2>;

			ranges;



			nvidia,num-lanes = <1>;

		};

	};



	host1x@13e00000 {

		compatible = "nvidia,tegra186-host1x", "simple-bus";

		reg = <0x0 0x13e00000 0x0 0x10000>,