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Commit f892f24b authored by Sean Paul's avatar Sean Paul Committed by Peter De Schrijver
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clk: tegra124: Add init data for dsi lp clocks 



Set the parent of the dsi lp clocks to pll_p and the rate
to 68MHz. The default parent is clk_m and rate is 12MHz, this
is too slow to receive data from the peripheral.

Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz
will suffice.

Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
parent 18abd163

drivers/clk/tegra/clk-tegra124.c

+2 −0
Original line number Diff line number Diff line
@@ -1368,6 +1368,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},

	{TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},

	{TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},

	{TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0},

	{TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0},

	{TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},

	{TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},

	{TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},