Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f780429a authored by Florian Fainelli's avatar Florian Fainelli
Browse files

soc: brcmstb: biuctrl: Move to early_initcall



Being called during early_initcall() is early enough that it occurs
before SMP initialization, which is all we care about for the Bus
Interface Unit configuration.

This solves lack of BIU initialization on ARM64 platforms where we do
not have an anchor where to put the BIU initialization (since there are
no machine descriptors).

Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent 5d4567ec
Loading
Loading
Loading
Loading
+0 −2
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@
#include <linux/init.h>
#include <linux/irqchip.h>
#include <linux/of_platform.h>
#include <linux/soc/brcmstb/brcmstb.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -38,7 +37,6 @@ u32 brcmstb_uart_config[3] = {
static void __init brcmstb_init_irq(void)
{
	irqchip_init();
	brcmstb_biuctrl_init();
}

static const char *const brcmstb_match[] __initconst = {
+4 −2
Original line number Diff line number Diff line
@@ -240,7 +240,7 @@ static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
#endif


void __init brcmstb_biuctrl_init(void)
static int __init brcmstb_biuctrl_init(void)
{
	int ret;

@@ -249,11 +249,13 @@ void __init brcmstb_biuctrl_init(void)
	ret = mcp_write_pairing_set();
	if (ret) {
		pr_err("MCP: Unable to disable write pairing!\n");
		return;
		return ret;
	}

	mcp_b53_set();
#ifdef CONFIG_PM_SLEEP
	register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
#endif
	return 0;
}
early_initcall(brcmstb_biuctrl_init);
+0 −6
Original line number Diff line number Diff line
@@ -12,12 +12,6 @@ static inline u32 BRCM_REV(u32 reg)
	return reg & 0xff;
}

/*
 * Bus Interface Unit control register setup, must happen early during boot,
 * before SMP is brought up, called by machine entry point.
 */
void brcmstb_biuctrl_init(void);

/*
 * Helper functions for getting family or product id from the
 * SoC driver.